Graphics processing systems
    1.
    发明授权

    公开(公告)号:US10937233B2

    公开(公告)日:2021-03-02

    申请号:US16518677

    申请日:2019-07-22

    Applicant: Arm Limited

    Abstract: Disclosed herein is a bounding box that can be generated for a set of one or more primitive(s) and then passed to a rasteriser circuit for use thereby when generating the graphics fragments to be processed. The bounding box generation integrates a scissor test and allows primitives for which an initial bounding box has zero intersection with a specified scissor box to be discarded, whereas for primitives whose initial bounding box does intersect the scissor box, a new bounding box can be generated for output based on the area of intersection.

    GRAPHICS PROCESSORS
    2.
    发明公开
    GRAPHICS PROCESSORS 审中-公开

    公开(公告)号:US20240169649A1

    公开(公告)日:2024-05-23

    申请号:US18509676

    申请日:2023-11-15

    Applicant: Arm Limited

    CPC classification number: G06T15/005 G06F9/4881 G06T15/40

    Abstract: When performing tile-based rendering a first, pre-pass operation in which primitives in a sequence of primitives for a tile are processed to determine visibility information for the sequence of primitives, the visibility information being usable to determine whether or not fragments for a primitive in the sequence of primitives should subsequently be processed further for the render output, is performed. Thereafter a second, main pass operation is performed in which the further processing of fragments for primitives that were processed during the first, pre-pass operation is controlled based on the determined visibility information for the sequence of primitives, such that for fragments for which the visibility information indicates that the fragments should not be processed further for the render output some or all of the processing during the second, main pass is omitted. Passes from different tiles can be interleaved.

    GRAPHICS PROCESSORS
    3.
    发明公开
    GRAPHICS PROCESSORS 审中-公开

    公开(公告)号:US20240169619A1

    公开(公告)日:2024-05-23

    申请号:US18509687

    申请日:2023-11-15

    Applicant: Arm Limited

    CPC classification number: G06T11/40 G06T1/20

    Abstract: When performing tile-based rendering a first, pre-pass operation in which primitives in a sequence of primitives for a tile are processed to determine visibility information for the sequence, the visibility information being usable to determine whether fragments for a primitive in the sequence should subsequently be processed further, is performed. Thereafter a second, main pass operation is performed in which the further processing of fragments for primitives that were processed during the first, pre-pass operation is controlled based on the determined visibility information for the sequence of primitives, such that for fragments for which the visibility information indicates that the fragments should not be processed further for the render output some or all of the processing during the second, main pass is omitted. The visibility information indicates which primitives should be rendered for which sampling positions of the render output in a hierarchical manner.

    GRAPHICS PROCESSING
    4.
    发明公开
    GRAPHICS PROCESSING 审中-公开

    公开(公告)号:US20240037853A1

    公开(公告)日:2024-02-01

    申请号:US18357481

    申请日:2023-07-24

    Applicant: Arm Limited

    CPC classification number: G06T17/20 G06T1/20

    Abstract: When performing tile-based rendering in a graphics processing system, lists indicative of fragments to be processed are maintained for respective sub-regions of tiles to be rendered, with each list entry representing a group of one or more fragments and including an indication of the coverage within the tile sub-region of the group of fragments that the list entry represents. The coverage information for the list entries is then used to set for entries in the list indicative of fragments to be processed for a sub-region, information indicating whether one or more processing operations are eligible to be performed for fragments that entries in the list represent.

    Full tile primitives in tile-based graphics processing

    公开(公告)号:US11361400B1

    公开(公告)日:2022-06-14

    申请号:US17313968

    申请日:2021-05-06

    Applicant: Arm Limited

    Abstract: A primitive that triggers performance of a graphics operation for the entirety of a tile is included in the sequence of primitives for a sequence of rendering tiles being provided to subsequent stages of the graphics processing pipeline for processing at least one tile in advance of the tile to which the primitive that is to trigger a graphics processing operation for the entirety of the tile relates. If, subsequent to the starting of the processing of the primitive that performs a processing operation for the entirety of the tile, it is determined that no other primitives will be processed for the tile, at least one of the subsequent processing stages of the graphics processing pipeline is caused to stop performing processing in respect of the primitive that performs a processing operation for the entirety of the tile.

    Graphics processing
    6.
    发明授权

    公开(公告)号:US11250611B1

    公开(公告)日:2022-02-15

    申请号:US17163281

    申请日:2021-01-29

    Applicant: Arm Limited

    Abstract: A method of operating a graphics processor that executes a graphics processing pipeline that can generate a render output using different shading rates is disclosed. First and second input shading rates are combined prior to rasterisation, and a combined shading rate may be propagated through the pipeline instead of the first and second input shading rates. The combined shading rate may then be combined with a third input shading rate at or after the rasterisation stage. This can reduce bandwidth, hardware and energy requirements.

    GRAPHICS PROCESSORS
    7.
    发明公开
    GRAPHICS PROCESSORS 审中-公开

    公开(公告)号:US20240169648A1

    公开(公告)日:2024-05-23

    申请号:US18509441

    申请日:2023-11-15

    Applicant: Arm Limited

    CPC classification number: G06T15/005 G06T11/40

    Abstract: When performing tile-based rendering a first, pre-pass operation in which primitives for a tile are processed to determine visibility information, the visibility information being usable to determine whether fragments for a primitive in the sequence of primitives should subsequently be processed further for the render output, is performed. Thereafter a second, main pass operation is performed in which the further processing of fragments for primitives that were processed during the first, pre-pass operation is controlled based on the determined visibility information for the sequence of primitives, such that for fragments for which the visibility information indicates that the fragments should not be processed further for the render output some or all of the processing during the second, main pass is omitted. The visibility information indicates which primitives should be rendered for which sampling positions of the render output in a hierarchical manner.

    GRAPHICS PROCESSORS
    8.
    发明公开
    GRAPHICS PROCESSORS 审中-公开

    公开(公告)号:US20240169647A1

    公开(公告)日:2024-05-23

    申请号:US18509439

    申请日:2023-11-15

    Applicant: Arm Limited

    CPC classification number: G06T15/005 G06T11/40

    Abstract: When performing tile-based rendering a first, pre-pass operation in which primitives in a sequence of primitives for a tile are processed to determine visibility information for the sequence of primitives, the visibility information being usable to determine whether or not fragments for a primitive in the sequence of primitives should subsequently be processed further for the render output, is performed. Thereafter a second, main pass operation is performed in which the further processing of fragments for primitives that were processed during the first, pre-pass operation is controlled based on the determined visibility information for the sequence of primitives, such that for fragments for which the visibility information indicates that the fragments should not be processed further for the render output some or all of the processing during the second, main pass is omitted. A data structure is also built to allow entire primitives to be culled.

    Graphics processing primitive patch testing

    公开(公告)号:US11321803B2

    公开(公告)日:2022-05-03

    申请号:US17010247

    申请日:2020-09-02

    Applicant: Arm Limited

    Abstract: A method of operating a tile-based graphics processor that can use one of plural different rendering tile sizes is disclosed. The tile-based graphics processor includes a rasteriser that can rasterise primitives in a hierarchical manner. A patch size at which to begin the hierarchical testing of primitives in the rasteriser is selected based on the rendering tile size that is to be used. This can reduce the overall number of tests performed to rasterise primitives without impacting the correct functioning of the hierarchical rasterisation process.

    GRAPHICS PROCESSING
    10.
    发明申请

    公开(公告)号:US20220067871A1

    公开(公告)日:2022-03-03

    申请号:US17010247

    申请日:2020-09-02

    Applicant: Arm Limited

    Abstract: A method of operating a tile-based graphics processor that can use one of plural different rendering tile sizes is disclosed. The tile-based graphics processor includes a rasteriser that can rasterise primitives in a hierarchical manner. A patch size at which to begin the hierarchical testing of primitives in the rasteriser is selected based on the rendering tile size that is to be used. This can reduce the overall number of tests performed to rasterise primitives without impacting the correct functioning of the hierarchical rasterisation process.

Patent Agency Ranking