公开(公告)号：US12131155B2

公开(公告)日：2024-10-29

申请号：US17597134

申请日：2020-03-25

Applicant: ARM LIMITED ,  THE CHANCELLOR, MASTERS AND SCHOLARS OF THE UNIVERSITY OF CAMBRIDGE

Inventor： Peng Sun ,  Timothy Martin Jones ,  Giacomo Gabrielli

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/355 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/3004 ,  G06F9/3555 ,  G06F9/3842

Abstract: An apparatus and method are provided for speculatively vectorising program code. The apparatus includes processing circuitry for executing program code, the program code including an identified code region comprising at least a plurality of speculative vector memory access instructions. Execution of each speculative vector memory access instruction is employed to perform speculative vectorisation of a series of scalar memory access operations using a plurality of lanes of processing. Tracking storage is used to maintain, for each speculative vector memory access instruction, tracking information providing an indication of a memory address being accessed within each lane. Checking circuitry then references the tracking information during execution of the identified code region by the processing circuitry, in order to detect any inter lane memory hazard resulting from the execution of the plurality of speculative vector memory access instructions.

公开(公告)号：US20250156184A1

公开(公告)日：2025-05-15

申请号：US18844296

申请日：2022-12-15

Applicant: Arm Limited

Inventor： Alejandro Martinez Vicente ,  Peng Sun

IPC: G06F9/30

Abstract: An apparatus has processing circuitry (16) to perform data processing, and instruction decoding circuitry (10) to control the processing circuitry to perform the data processing in response to decoding of program instructions defined according to a scalable vector instruction set architecture supporting vector instructions operating on vectors of scalable vector length to enable the same instruction sequence to be executed on apparatuses with hardware supporting different maximum vector lengths. The instruction decoding circuitry and the processing circuitry support a sub-vector-supporting instruction which treats a given vector as comprising a plurality of sub-vectors with each sub-vector comprising a plurality of vector elements. In response to the sub-vector-supporting instruction, the instruction decoding circuitry controls the processing circuitry to perform an operation for the given vector at sub-vector granularity. Each sub-vector has an equal sub-vector length.