公开(公告)号：US20250087296A1

公开(公告)日：2025-03-13

申请号：US18243441

申请日：2023-09-07

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Khushal Gelda ,  Ramesh Manohar ,  Teresa Louise Mclaurin ,  Prashant Mohan Kulkarni

IPC: G11C29/00 ,  G11C29/18 ,  G11C29/44

Abstract: Various implementations described herein are directed to a device having a bank of bitcells split into a plurality of portions including a first row slice of the bitcells and a second row slice of the bitcells. Also, the device may have control circuitry configured to access and repair a first bitcell in the first row slice with a first row address and a second bitcell in the second row slice with a second row address that is different than the first row address.