公开(公告)号：US12300338B2

公开(公告)日：2025-05-13

申请号：US17953271

申请日：2022-09-26

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Vianney Antoine Choserot ,  Yew Keong Chong ,  Khushal Gelda

IPC: G11C29/32 ,  G11C29/12 ,  G11C29/54

Abstract: Various implementations described herein are related to a device having first datapath circuitry with input devices that receive data from a number of write ports and provide first data. The device may have second datapath circuitry with logic gates that receive the first data from the input devices and provide the first data based on a read bitline signal. The device may have third datapath circuitry with output devices that receive the first data from the logic gates and provide second data to a number of read ports. Also, the number of read ports is greater than the number of write ports.

公开(公告)号：US20240219955A1

公开(公告)日：2024-07-04

申请号：US18091719

申请日：2022-12-30

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan ,  Akash Bangalore Srinivasa ,  Munish Kumar ,  Khushal Gelda ,  Akshay Kumar

IPC: G06F1/10 ,  G06F1/06 ,  G06F11/30

CPC classification number: G06F1/10 ,  G06F1/06 ,  G06F11/3062

Abstract: Various implementations described herein are related to a device having multi-port circuit architecture with multiple ports. The multi-port circuit architecture may expand a primary clock into multiple dummy clocks so as to separately track, simulate and report clock power consumption for each port of the multiple ports to a central processing unit.

公开(公告)号：US20250087296A1

公开(公告)日：2025-03-13

申请号：US18243441

申请日：2023-09-07

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Khushal Gelda ,  Ramesh Manohar ,  Teresa Louise Mclaurin ,  Prashant Mohan Kulkarni

IPC: G11C29/00 ,  G11C29/18 ,  G11C29/44

Abstract: Various implementations described herein are directed to a device having a bank of bitcells split into a plurality of portions including a first row slice of the bitcells and a second row slice of the bitcells. Also, the device may have control circuitry configured to access and repair a first bitcell in the first row slice with a first row address and a second bitcell in the second row slice with a second row address that is different than the first row address.

公开(公告)号：US12066855B2

公开(公告)日：2024-08-20

申请号：US18091719

申请日：2022-12-30

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan ,  Akash Bangalore Srinivasa ,  Munish Kumar ,  Khushal Gelda ,  Akshay Kumar

IPC: G06F1/00 ,  G06F1/06 ,  G06F1/10 ,  G06F11/30

CPC classification number: G06F1/10 ,  G06F1/06 ,  G06F11/3062

Abstract: Various implementations described herein are related to a device having multi-port circuit architecture with multiple ports. The multi-port circuit architecture may expand a primary clock into multiple dummy clocks so as to separately track, simulate and report clock power consumption for each port of the multiple ports to a central processing unit.

公开(公告)号：US11521703B2

公开(公告)日：2022-12-06

申请号：US17218927

申请日：2021-03-31

Applicant: Arm Limited

Inventor： Amandeep Kaur ,  Andy Wangkun Chen ,  Penaka Phani Goberu ,  Khushal Gelda

IPC: G11C29/00 ,  G11C29/44 ,  G01R31/3193

Abstract: Various implementations described herein are related to a method for identifying multi-bank memory architecture having multiple banks including a first bank and a second bank. The method may receive a faulty row address having a faulty bank selection bit, and also, the method may select the first bank or the second bank for row redundancy operations based on the faulty bank selection bit.

公开(公告)号：US20220319632A1

公开(公告)日：2022-10-06

申请号：US17218927

申请日：2021-03-31

Applicant: Arm Limited

Inventor： Amandeep Kaur ,  Andy Wangkun Chen ,  Penaka Phani Goberu ,  Khushal Gelda

IPC: G11C29/00 ,  G01R31/3193 ,  G11C29/44

Abstract: Various implementations described herein are related to a method for identifying multi-bank memory architecture having multiple banks including a first bank and a second bank. The method may receive a faulty row address having a faulty bank selection bit, and also, the method may select the first bank or the second bank for row redundancy operations based on the faulty bank selection bit.