公开(公告)号：US20250087296A1

公开(公告)日：2025-03-13

申请号：US18243441

申请日：2023-09-07

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Khushal Gelda ,  Ramesh Manohar ,  Teresa Louise Mclaurin ,  Prashant Mohan Kulkarni

IPC: G11C29/00 ,  G11C29/18 ,  G11C29/44

Abstract: Various implementations described herein are directed to a device having a bank of bitcells split into a plurality of portions including a first row slice of the bitcells and a second row slice of the bitcells. Also, the device may have control circuitry configured to access and repair a first bitcell in the first row slice with a first row address and a second bitcell in the second row slice with a second row address that is different than the first row address.

公开(公告)号：US09651620B2

公开(公告)日：2017-05-16

申请号：US14531512

申请日：2014-11-03

Applicant: ARM LIMITED

Inventor： Ramesh Manohar ,  James Dennis Dodrill

IPC: G01R27/28 ,  G01R31/3183 ,  H03K3/03

CPC classification number: G01R31/318328 ,  H03K3/0315

Abstract: A measurement circuit and method is provided for generating an oscillating output signal used to derive timing information. The measurement circuit includes a ring oscillator having a plurality of unit cells, where each unit cell comprises at least a storage element whose output signal is used to determine a clock input signal for an adjacent unit cell within the ring oscillator. Control circuitry performs a control operation to control either a set function or a reset function of the storage element in each of the unit cells, in dependence on set or reset signals input to the control circuitry. Oscillation initiation circuitry is used to assert a clock input signal to the storage element in a first unit cell in order to initiate generation of the oscillating output signal, and the control circuitry then performs the control operation in order to control a value of the output signal of the storage element in each unit cell so as to cause the oscillating output signal to be maintained. Such an approach provides a particularly simple and efficient mechanism for deriving timing information for various circuit blocks that include a storage element.

公开(公告)号：US20240329153A1

公开(公告)日：2024-10-03

申请号：US18127871

申请日：2023-03-29

Applicant: Arm Limited

Inventor： Ashwani Kumar Srivastava ,  Yves Thomas Laplanche ,  Ramesh Manohar

IPC: G01R31/52

CPC classification number: G01R31/52

Abstract: Various implementations described herein are related to a device with fabrication test circuitry having transistors arranged in a parallel branch configuration between a supply voltage and a single pad. In some applications, each transistor in an off-current branch may be separately deactivated so as to test leakage current applied to the pad by way of the off-current branch, and also, each transistor in an on-current branch may be deactivated so as to further test the leakage current applied to the pad by way of the off-current branch.