公开(公告)号：US10942878B1

公开(公告)日：2021-03-09

申请号：US16831266

申请日：2020-03-26

Applicant: Arm Limited

Inventor： Sean James Salisbury ,  Chiranjeev Acharya ,  Eduard Vardanyan ,  Premkishore Shivakumar

IPC: G06F13/28 ,  G06F9/46

Abstract: An on-chip interconnect comprises control circuitry which responds to a burst read request received at an initiating requester interface, to control issuing of at least one read request to at least one target completer device via at least one target completer interface. For a chunking enabled burst read transaction, the control circuitry supports returning the requested data items to the initiating requester device in a number of data transfers, with an order of the data items in the data transfers permitted to differ from a default order and each data transfer specifying chunk identifying information identifying which portion of the data items is represented by returned data for that data transfer. For a data transfer returned to the initiating requester device based on data returned from one of a second subset of completer interfaces, the control circuitry generates the chunk identifying information to be specified by the given data transfer.

公开(公告)号：US12057947B1

公开(公告)日：2024-08-06

申请号：US18115301

申请日：2023-02-28

Applicant: Arm Limited

Inventor： Sean Allan Steel ,  David Yue Williams ,  Premkishore Shivakumar

IPC: H04L1/00 ,  H04L1/24

CPC classification number: H04L1/245

Abstract: In a data processing network, error detection information (EDI) is generated for first data of a first communication protocol of a plurality of communication protocols, the EDI including an error detection code and an associated validity indicator for each field group in a set of field groups. The first data and the EDI are sent through a network interconnect circuit, where the first data is translated to second data of a second communication protocol. An error is detected in the second data received from the network interconnect circuit when a validity indicator for a field group is set in EDI received with the second data and an error detection code generated for second data in the field group does not match the error detection code associated with the field group in the received EDI.

公开(公告)号：US11531620B2

公开(公告)日：2022-12-20

申请号：US17212804

申请日：2021-03-25

Applicant: Arm Limited

Inventor： Kishore Kumar Jagadeesha ,  Jamshed Jalal ,  Tushar P Ringe ,  Mark David Werkheiser ,  Premkishore Shivakumar ,  Lauren Elise Guckert

IPC: G06F12/0815 ,  G06F12/0831 ,  G06F13/40

Abstract: A data processing network includes request nodes with local memories accessible as a distributed virtual memory (DVM) and coupled by an interconnect fabric. Multiple DVM domains are assigned, each containing a DVM node for handling DVM operation requests from request nodes in the domain. On receipt of a request, a DVM node sends a snoop message to other request nodes in its domain and sends a snoop message to one or more peer DVM nodes in other DVM domains. The DVM node receives snoop responses from the request nodes and from the one or more peer DVM nodes, and send a completion message to the first request node. Each peer DVM node sends snoop messages to the request nodes in its domain, collects snoop responses, and sends a single response to the originating DVM node. In this way, DVM operations are performed in parallel.

公开(公告)号：US20220308997A1

公开(公告)日：2022-09-29

申请号：US17212804

申请日：2021-03-25

Applicant: Arm Limited

Inventor： Kishore Kumar Jagadeesha ,  Jamshed Jalal ,  Tushar P Ringe ,  Mark David Werkheiser ,  Premkishore Shivakumar ,  Lauren Elise Guckert

IPC: G06F12/0815 ,  G06F13/40

Abstract: A data processing network includes request nodes with local memories accessible as a distributed virtual memory (DVM) and coupled by an interconnect fabric. Multiple DVM domains are assigned, each containing a DVM node for handling DVM operation requests from request nodes in the domain. On receipt of a request, a DVM node sends a snoop message to other request nodes in its domain and sends a snoop message to one or more peer DVM nodes in other DVM domains. The DVM node receives snoop responses from the request nodes and from the one or more peer DVM nodes, and send a completion message to the first request node. Each peer DVM node sends snoop messages to the request nodes in its domain, collects snoop responses, and sends a single response to the originating DVM node. In this way, DVM operations are performed in parallel.

公开(公告)号：US20240291599A1

公开(公告)日：2024-08-29

申请号：US18115301

申请日：2023-02-28

Applicant: Arm Limited

Inventor： Sean Allan Steel ,  David Yue Williams ,  Premkishore Shivakumar

IPC: H04L1/24

CPC classification number: H04L1/245

Abstract: In a data processing network, error detection information (EDI) is generated for first data of a first communication protocol of a plurality of communication protocols, the EDI including an error detection code and an associated validity indicator for each field group in a set of field groups. The first data and the EDI are sent through a network interconnect circuit, where the first data is translated to second data of a second communication protocol. An error is detected in the second data received from the network interconnect circuit when a validity indicator for a field group is set in EDI received with the second data and an error detection code generated for second data in the field group does not match the error detection code associated with the field group in the received EDI.

公开(公告)号：US10698825B1

公开(公告)日：2020-06-30

申请号：US16299291

申请日：2019-03-12

Applicant: Arm Limited

Inventor： Gurunath Ramagiri ,  Ashok Kumar Tummala ,  Mark David Werkheiser ,  Jamshed Jalal ,  Premkishore Shivakumar ,  Paul Gilbert Meyer

IPC: G06F12/00 ,  G06F12/0817 ,  G06F16/901

Abstract: In a system-on-chip there is a local interconnect to connect local devices on the chip to one another, a gateway to connect the chip to a remote chip of a plurality of chips in a cache-coherent multi-chip system via an inter-chip interconnect, and a cache-coherent device. The cache-coherent device has a cache-coherency look-up table having entries for shared cache data lines. When a data access request is received via the inter-chip interconnect and the local interconnect a system-unique identifier for a request source of the data access request is generated in dependence on an inter-chip request source identifier used on the inter-chip interconnect and an identifier indicative of the remote chip. The bit-set used to express the system-unique identifier is larger than the bit-set used to express the inter-chip request source identifier. The system-unique identifier is used with respect to the cache-coherency look-up table to perform the cache-coherency actions for the cache line enabling more cache coherent devices to be supported.