利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

12 条记录 (耗时 0.011 秒)

    Access control
    1.
    发明授权
    Access control 有权

    公开(公告)号：US10324858B2

    公开(公告)日：2019-06-18

    申请号：US15620017

    申请日：2017-06-12

    申请人： ARM LIMITED

    发明人： Bruce James Mathewson ,  Phanindra Kumar Mannava ,  Matthew Lucien Evans ,  Paul Gilbert Meyer ,  Andrew Brookfield Swaine

    IPC分类号： G06F12/10 ,  G06F12/1036 ,  G06F12/0802 ,  G06F12/14 ,  G06F13/16

    摘要： Access control circuitry comprises: a detector to detect a memory address translation between a virtual memory address in a virtual memory address space and a physical memory address in a physical memory address space, provided in response to a translation request by further circuitry; an address translation memory, to store data representing a set of physical memory addresses previously provided to the further circuitry in response to translation requests by the further circuitry; an interface to receive a physical memory address from the further circuitry for a memory access by the further circuitry; a comparator to compare a physical memory address received from the further circuitry with the set of physical addresses stored by the address translation memory, and to permit access, by the further circuitry, to a physical address included in the set of one or more physical memory addresses.

    Error detection circuitry for use with memory
    2.
    发明授权
    Error detection circuitry for use with memory 有权

    公开(公告)号：US09891976B2

    公开(公告)日：2018-02-13

    申请号：US14633062

    申请日：2015-02-26

    申请人： ARM Limited

    发明人： Andy Wangkun Chen ,  Mudit Bhargava ,  Paul Gilbert Meyer ,  Vikas Chandra

    IPC分类号： G06F11/10 ,  G06F11/07 ,  G06F11/08

    CPC分类号： G06F11/076 ,  G06F11/085 ,  G06F11/1012 ,  G06F11/1016

    摘要： Various implementations described herein may refer to and may be directed to error detection circuitry for use with memory. In one implementation, an integrated circuit may include a memory array having a plurality of rows of memory cells, where a respective row is configured to store a data word and one or more check bits corresponding to the data word. The integrated circuit may also include inline error detection circuitry coupled to the respective row and configured to generate one or more flag bit values based on a detection of one or more bit errors in the data word stored in the respective row. The integrated circuit may further include error correction circuitry configured to correct the one or more bit errors in the data word stored in the respective row in response to the one or more generated flag bit values.

    Cache content management
    3.
    发明授权
    Cache content management 有权

    公开(公告)号：US11256623B2

    公开(公告)日：2022-02-22

    申请号：US15427459

    申请日：2017-02-08

    申请人： ARM Limited

    发明人： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal ,  Klas Magnus Bruce ,  Michael Filippo ,  Paul Gilbert Meyer ,  Alex James Waugh ,  Geoffray Matthieu Lacourba

    IPC分类号： G06F12/0831 ,  G06F12/0808

    摘要： Apparatus and a corresponding method of operating a hub device, and a target device, in a coherent interconnect system are presented. A cache pre-population request of a set of coherency protocol transactions in the system is received from a requesting master device specifying at least one data item and the hub device responds by cause a cache pre-population trigger of the set of coherency protocol transactions specifying the at least one data item to be transmitted to a target device. This trigger can cause the target device to request that the specified at least one data item is retrieved and brought into cache. Since the target device can therefore decide whether to respond to the trigger or not, it does not receive cached data unsolicited, simplifying its configuration, whilst still allowing some data to be pre-cached.

    Apparatus and method for processing an ownership upgrade request for cached data that is issued in relation to a conditional store operation
    4.
    发明授权
    Apparatus and method for processing an ownership upgrade request for cached data that is issued in relation to a conditional store operation 有权

    公开(公告)号：US10761987B2

    公开(公告)日：2020-09-01

    申请号：US16202171

    申请日：2018-11-28

    申请人： Arm Limited

    发明人： Jamshed Jalal ,  Mark David Werkheiser ,  Michael Filippo ,  Klas Magnus Bruce ,  Paul Gilbert Meyer

    IPC分类号： G06F12/0815 ,  G06F13/16

    摘要： An apparatus and method are provided for processing ownership upgrade requests in relation to cached data. The apparatus has a plurality of processing units, at least some of which have associated cache storage. A coherent interconnect couples the plurality of master units with memory, the coherent interconnect having a snoop unit used to implement a cache coherency protocol when a request received by the coherent interconnect identifies a cacheable memory address within the memory. Contention management circuitry is provided to control contended access to a memory address by two or more processing units within the plurality of processing units. The coherent interconnect may receive, from a first processing unit having an associated cache storage, an ownership upgrade request specifying a target memory address, the ownership upgrade request indicating that a copy of data at the target memory address, as held in a shared state in the first processing unit's associated cache storage at a time the ownership upgrade request was issued, is required to have its state changed from the shared state to a unique state prior to the first processing circuitry performing a write operation to the data. The coherent interconnect is arranged to process the ownership upgrade request by referencing the snoop unit in order to determine whether the first processing unit's associated cache storage is identified as still holding a copy of the data at the target memory address at a time the ownership upgrade request is processed. In that event, a pass condition is identified for the ownership upgrade request independent of information held by the contention management circuitry for the target memory address.

    Inter-chip communication in a multi-chip system
    6.
    发明授权
    Inter-chip communication in a multi-chip system 有权

    公开(公告)号：US10698825B1

    公开(公告)日：2020-06-30

    申请号：US16299291

    申请日：2019-03-12

    申请人： Arm Limited

    发明人： Gurunath Ramagiri ,  Ashok Kumar Tummala ,  Mark David Werkheiser ,  Jamshed Jalal ,  Premkishore Shivakumar ,  Paul Gilbert Meyer

    IPC分类号： G06F12/00 ,  G06F12/0817 ,  G06F16/901

    摘要： In a system-on-chip there is a local interconnect to connect local devices on the chip to one another, a gateway to connect the chip to a remote chip of a plurality of chips in a cache-coherent multi-chip system via an inter-chip interconnect, and a cache-coherent device. The cache-coherent device has a cache-coherency look-up table having entries for shared cache data lines. When a data access request is received via the inter-chip interconnect and the local interconnect a system-unique identifier for a request source of the data access request is generated in dependence on an inter-chip request source identifier used on the inter-chip interconnect and an identifier indicative of the remote chip. The bit-set used to express the system-unique identifier is larger than the bit-set used to express the inter-chip request source identifier. The system-unique identifier is used with respect to the cache-coherency look-up table to perform the cache-coherency actions for the cache line enabling more cache coherent devices to be supported.

    Cache maintenance operations in a data processing system
    9.
    发明授权
    Cache maintenance operations in a data processing system 有权

    公开(公告)号：US10783080B2

    公开(公告)日：2020-09-22

    申请号：US16173213

    申请日：2018-10-29

    申请人： Arm Limited

    发明人： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal ,  Paul Gilbert Meyer

    IPC分类号： G06F12/08 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/1009 ,  G06F3/06 ,  G06F9/52

    摘要： An interconnect system and method of operating the system are disclosed. A master device has access to a cache and a slave device has an associated data storage device for long-term storage of data items. The master device can initiate a cache maintenance operation in the interconnect system with respect to a data item temporarily stored in the cache causing action to be taken by the slave device with respect to storage of the data item in the data storage device. For long latency operations the master device can issue a separated cache maintenance request specifying the data item and the slave device. In response an intermediate device signals an acknowledgment response indicating that it has taken on responsibility for completion of the cache maintenance operation and issues the separated cache maintenance request to the slave device. The slave device signals the acknowledgement response to the intermediate device and on completion of the cache maintenance operation with respect to the data item stored in the data storage device signals a completion response to the master device.