公开(公告)号：US20240273026A1

公开(公告)日：2024-08-15

申请号：US18109454

申请日：2023-02-14

Applicant: Arm Limited

Inventor： Devi Sravanthi Yalamarthy ,  Jamshed Jalal ,  Mark David Werkheiser ,  Wenxuan Zhang ,  Ritukar Khanna ,  Rajani Pai ,  Gurunath Ramagiri ,  Mukesh Patel ,  Tushar P Ringe

IPC: G06F12/084 ,  G06F12/0811 ,  G06F12/0891

CPC classification number: G06F12/084 ,  G06F12/0811 ,  G06F12/0891

Abstract: A data processing apparatus includes one or more cache configuration data stores, a coherence manager, and a shared cache. The coherence manager is configured to track and maintain coherency of cache lines accessed by local caching agents and one or more remote caching agents. The cache lines include local cache lines accessed from a local memory region and remote cache lines accessed from a remote memory region. The shared cache is configured to store local cache lines in a first partition and to store remote cache lines in a second partition. The sizes of the first and second partitions are determined based on values in the one or more cache configuration data stores and may or not overlap. The cache configuration data stores may be programmable by a user or dynamically programmed in response to local memory and remote memory access patterns.