公开(公告)号：US11593025B2

公开(公告)日：2023-02-28

申请号：US16743409

申请日：2020-01-15

申请人： Arm Limited

发明人： Gurunath Ramagiri ,  Jamshed Jalal ,  Mark David Werkheiser ,  Tushar P Ringe ,  Klas Magnus Bruce ,  Ritukar Khanna

IPC分类号： G06F3/06

摘要： A request node is provided comprising request circuitry to issue write requests to write data to storage circuitry. The write requests are issued to the storage circuitry via a coherency node. Status receiving circuitry receives a write status regarding write operations at the storage circuitry from the coherency node and throttle circuitry throttles a rate at which the write requests are issued to the storage circuitry in dependence on the write status. A coherency node is also provided, comprising access circuitry to receive a write request from a request node to write data to storage circuitry and to access the storage circuitry to write the data to the storage circuitry. Receive circuitry receives, from the storage circuitry, an incoming write status regarding write operations at the storage circuitry and transmit circuitry transmits an outgoing write status to the request node based on the incoming write status.

公开(公告)号：US20240273025A1

公开(公告)日：2024-08-15

申请号：US18109453

申请日：2023-02-14

申请人： Arm Limited

发明人： Wenxuan Zhang ,  Jamshed Jalal ,  Mark David Werkheiser ,  Sakshi Verma ,  Ritukar Khanna ,  Devi Sravanthi Yalamarthy ,  Gurunath Ramagiri ,  Mukesh Patel ,  Tushar P Ringe

IPC分类号： G06F12/0831 ,  G06F12/0871

CPC分类号： G06F12/0833 ,  G06F12/0871

摘要： A super home node of a first chip of a multi-chip data processing system manages coherence for both local and remote cache lines accessed by local caching agents and local cache lines accessed by caching agents of one or more second chips. Both local and remote cache lines are stored in a shared cache, and requests are stored in shared point-of-coherency queue. An entry in a snoop filter table of the super home node includes a presence vector that indicates the presence of a remote cache line at specific caching agents of the first chip or the presence of a local cache line at specific caching agents of the first chip and any caching agent of the second chip. All caching agents of the second chip are represented as a single caching agent in the presence vector.

公开(公告)号：US20240273026A1

公开(公告)日：2024-08-15

申请号：US18109454

申请日：2023-02-14

申请人： Arm Limited

发明人： Devi Sravanthi Yalamarthy ,  Jamshed Jalal ,  Mark David Werkheiser ,  Wenxuan Zhang ,  Ritukar Khanna ,  Rajani Pai ,  Gurunath Ramagiri ,  Mukesh Patel ,  Tushar P Ringe

IPC分类号： G06F12/084 ,  G06F12/0811 ,  G06F12/0891

CPC分类号： G06F12/084 ,  G06F12/0811 ,  G06F12/0891

摘要： A data processing apparatus includes one or more cache configuration data stores, a coherence manager, and a shared cache. The coherence manager is configured to track and maintain coherency of cache lines accessed by local caching agents and one or more remote caching agents. The cache lines include local cache lines accessed from a local memory region and remote cache lines accessed from a remote memory region. The shared cache is configured to store local cache lines in a first partition and to store remote cache lines in a second partition. The sizes of the first and second partitions are determined based on values in the one or more cache configuration data stores and may or not overlap. The cache configuration data stores may be programmable by a user or dynamically programmed in response to local memory and remote memory access patterns.