公开(公告)号：US10452575B1

公开(公告)日：2019-10-22

申请号：US16055211

申请日：2018-08-06

Applicant: Arm Limited

Inventor： Tushar P. Ringe ,  Jamshed Jalal ,  Mark David Werkheiser ,  Glenn Allan Canto ,  Ashok Kumar Tummala ,  Devi Sravanthi Yalamarthy

IPC: G06F3/00 ,  G06F13/16 ,  G06F3/06

Abstract: A system, apparatus and method for ordering a sequence of processing transactions for a plurality of peripheral units. The sequence of transactions is accomplished by mapping an incoming address to a target endpoint. The ordering of the transactions is agnostic to the type of endpoint being targeted and only considers an identifier of the transaction for ordering purposes.

公开(公告)号：US20240273026A1

公开(公告)日：2024-08-15

申请号：US18109454

申请日：2023-02-14

Applicant: Arm Limited

Inventor： Devi Sravanthi Yalamarthy ,  Jamshed Jalal ,  Mark David Werkheiser ,  Wenxuan Zhang ,  Ritukar Khanna ,  Rajani Pai ,  Gurunath Ramagiri ,  Mukesh Patel ,  Tushar P Ringe

IPC: G06F12/084 ,  G06F12/0811 ,  G06F12/0891

CPC classification number: G06F12/084 ,  G06F12/0811 ,  G06F12/0891

Abstract: A data processing apparatus includes one or more cache configuration data stores, a coherence manager, and a shared cache. The coherence manager is configured to track and maintain coherency of cache lines accessed by local caching agents and one or more remote caching agents. The cache lines include local cache lines accessed from a local memory region and remote cache lines accessed from a remote memory region. The shared cache is configured to store local cache lines in a first partition and to store remote cache lines in a second partition. The sizes of the first and second partitions are determined based on values in the one or more cache configuration data stores and may or not overlap. The cache configuration data stores may be programmable by a user or dynamically programmed in response to local memory and remote memory access patterns.

公开(公告)号：US20240273025A1

公开(公告)日：2024-08-15

申请号：US18109453

申请日：2023-02-14

Applicant: Arm Limited

Inventor： Wenxuan Zhang ,  Jamshed Jalal ,  Mark David Werkheiser ,  Sakshi Verma ,  Ritukar Khanna ,  Devi Sravanthi Yalamarthy ,  Gurunath Ramagiri ,  Mukesh Patel ,  Tushar P Ringe

IPC: G06F12/0831 ,  G06F12/0871

CPC classification number: G06F12/0833 ,  G06F12/0871

Abstract: A super home node of a first chip of a multi-chip data processing system manages coherence for both local and remote cache lines accessed by local caching agents and local cache lines accessed by caching agents of one or more second chips. Both local and remote cache lines are stored in a shared cache, and requests are stored in shared point-of-coherency queue. An entry in a snoop filter table of the super home node includes a presence vector that indicates the presence of a remote cache line at specific caching agents of the first chip or the presence of a local cache line at specific caching agents of the first chip and any caching agent of the second chip. All caching agents of the second chip are represented as a single caching agent in the presence vector.

公开(公告)号：US11074206B1

公开(公告)日：2021-07-27

申请号：US17036225

申请日：2020-09-29

Applicant: Arm Limited

Inventor： Jamshed Jalal ,  Tushar P Ringe ,  Kishore Kumar Jagadeesha ,  Ashok Kumar Tummala ,  Rishabh Jain ,  Devi Sravanthi Yalamarthy

IPC: G06F13/28 ,  G06F13/40 ,  G06F9/46

Abstract: The present disclosure advantageously provides a method and system for transferring data over at least one interconnect. A request node, coupled to an interconnect, receives a first write burst from a first device over a first connection, divides the first write burst into an ordered sequence of smaller write requests based on the size of the first write burst, and sends the ordered sequence of write requests to a home node coupled to the interconnect. The home node generates an ordered sequence of write transactions based on the ordered sequence of write requests, and sends the ordered sequence of write transactions to a write combiner coupled to the home node. The write combiner combines the ordered sequence of write transactions into a second write burst that is the same size as the first write burst, and sends the second write burst to a second device over a second connection.