公开(公告)号：US10824468B2

公开(公告)日：2020-11-03

申请号：US16273448

申请日：2019-02-12

Applicant: Arm Limited

Inventor： Mark Underwood ,  Sandeep Kakarlapudi ,  Robert John Rees

IPC: G06F9/46 ,  G06F9/48 ,  G06F12/0837 ,  G06F9/38 ,  G06F9/52

Abstract: A method of controlling a data processor to perform data processing operations is disclosed in which a host processor prepares one or more queue(s) of operations for execution by the data processor. When an error is encountered in the processing of an operation for one of the one or more queue(s), a queue can be set into an error state in which instructions that may have a data dependency on another operation are not executed. The host processor includes in the queues error barrier instructions that divide the respective queues into sets of operations between which there are no data processing dependencies. An error state for a queue can thus be cleared when its processing reaches the next error barrier instruction in the queue.

公开(公告)号：US20190056955A1

公开(公告)日：2019-02-21

申请号：US16047336

申请日：2018-07-27

Applicant: Arm Limited

Inventor： Jussi Tuomas Pennala ,  Robert John Rees ,  Hakan Lars-Goran Persson

IPC: G06F9/38 ,  G06F9/455 ,  G06F9/50

Abstract: A data processing system comprises one or more data processing units, a configurable interconnect and control circuitry. The control circuitry allocates one or more of the data processing units to a virtual machine and configures the configurable interconnect so as route one or more data processing tasks from the virtual machine to the one or more data processing units allocated for use by that virtual machine. This can provide a flexible and adaptable data processing system for carrying out the data processing tasks of a virtual machine, with the particular allocation of data processing units being substantially transparent to the virtual machine.

公开(公告)号：US20200257555A1

公开(公告)日：2020-08-13

申请号：US16273448

申请日：2019-02-12

Applicant: Arm Limited

Inventor： Mark Underwood ,  Sandeep Kakarlapudi ,  Robert John Rees

IPC: G06F9/48 ,  G06F9/52 ,  G06F9/38 ,  G06F12/0837

Abstract: A method of controlling a data processor to perform data processing operations is disclosed in which a host processor prepares one or more queue(s) of operations for execution by the data processor. When an error is encountered in the processing of an operation for one of the one or more queue(s), a queue can be set into an error state in which instructions that may have a data dependency on another operation are not executed. The host processor includes in the queues error barrier instructions that divide the respective queues into sets of operations between which there are no data processing dependencies. An error state for a queue can thus be cleared when its processing reaches the next error barrier instruction in the queue.

公开(公告)号：US10732982B2

公开(公告)日：2020-08-04

申请号：US16047336

申请日：2018-07-27

Applicant: Arm Limited

Inventor： Jussi Tuomas Pennala ,  Robert John Rees ,  Hakan Lars-Goran Persson

IPC: G06F9/46 ,  G06F9/38 ,  G06F9/455 ,  G06F9/50

Abstract: A data processing system comprises one or more data processing units, a configurable interconnect and control circuitry. The control circuitry allocates one or more of the data processing units to a virtual machine and configures the configurable interconnect so as route one or more data processing tasks from the virtual machine to the one or more data processing units allocated for use by that virtual machine. This can provide a flexible and adaptable data processing system for carrying out the data processing tasks of a virtual machine, with the particular allocation of data processing units being substantially transparent to the virtual machine.