公开(公告)号：US20240045653A1

公开(公告)日：2024-02-08

申请号：US17878277

申请日：2022-08-01

Applicant: Arm Limited

Inventor： Neil Burgess ,  Sangwon Ha ,  Partha Prasun Maji

IPC: G06F5/01

CPC classification number: G06F5/012

Abstract: An apparatus and method of converting data into an Enhanced Block Floating Point (EBFP) format with a shared exponent is provided. The EBFP format enables data within a wide range of values to be stored using a reduced number of bits compared with conventional floating-point or fixed-point formats. The data to be converted may be in any other format, such as fixed-point, floating-point, block floating-point or EBFP.

公开(公告)号：US20240036824A1

公开(公告)日：2024-02-01

申请号：US18213469

申请日：2023-06-23

Applicant: Arm Limited

Inventor： Neil Burgess ,  Sangwon Ha ,  Partha Prasun Maji

IPC: G06F7/499

CPC classification number: G06F7/49947 ,  G06F7/49915

Abstract: In a data processor, an input value having a sign, an exponent and a significand is encoded by determining an exponent difference between a base exponent and the exponent. When the exponent difference is not less than a first threshold, only the exponent difference, or a designated value, is encoded to a payload of the output value and one or more tag bits of the output value are set to a first value. When the exponent difference is less than the first threshold, the significand and exponent difference are encoded to the payload of an output value and, optionally, the one or more tag bits of the output value. A sign bit in the output value is set corresponding to the sign of the input value, and the output value is stored.

公开(公告)号：US20240036822A1

公开(公告)日：2024-02-01

申请号：US17878291

申请日：2022-08-01

Applicant: Arm Limited

Inventor： Neil Burgess ,  Sangwon Ha ,  Partha Prasun Maji

IPC: G06F7/487 ,  G06F9/30

CPC classification number: G06F7/4876 ,  G06F9/3016

Abstract: A data processing apparatus is configured to determine a product of two operands stored in an Extended Block Floating-Point format. The operands are decoded, based on their tags and payloads, to generate exponent differences and at least the fractional parts of significands. The significands are multiplied to generate an output significand and shared exponents and exponent differences of the operands are combined to generate an output exponent. Signs of the operands may also be combined to provide an output sign. The apparatus may be combined with an accumulator having one or more lanes to provide an apparatus for determining dot products.

公开(公告)号：US20240036821A1

公开(公告)日：2024-02-01

申请号：US18199151

申请日：2023-05-18

Applicant: Arm Limited

Inventor： Neil Burgess ,  Sangwon Ha ,  Partha Prasun Maji

IPC: G06F7/483

CPC classification number: G06F7/483

Abstract: In a data processor, an input datum, having a sign, a tag and a payload, is decoded by first determining a format of the payload based on the tag. For a first format, an exponent difference and an output fraction are decoded from the payload. For a second format, an exponent difference is decoded from the payload and the output fraction may be assumed to be zero. The exponent difference is subtracted from a shared exponent to produce the output exponent. The decoded output may be stored in a standard format for floating-point numbers.