公开(公告)号：US11836432B2

公开(公告)日：2023-12-05

申请号：US17091229

申请日：2020-11-06

Applicant: Arm Limited

Inventor： Sharath Koodali Edathil ,  Marlin Wayne Frederick, Jr.

IPC: G06F30/398 ,  G06F30/373 ,  G06F30/327 ,  G06F30/394

CPC classification number: G06F30/373 ,  G06F30/327 ,  G06F30/394 ,  G06F30/398

Abstract: Various implementations described herein refer to a method. The method may be configured to synthesize standard cells for a physical design having a power supply net with power supply rails. The method may be configured to employ a place-and-route tool so as to define edge-types for each standard cell of the standard cells in the physical design based on the power supply net and the power supply rails that touch at least one edge of each standard cell of the standard cells.

公开(公告)号：US20220188496A1

公开(公告)日：2022-06-16

申请号：US17685166

申请日：2022-03-02

Applicant: Arm Limited

Inventor： Sharath Koodali Edathil ,  Marlin Wayne Frederick, JR.

IPC: G06F30/373 ,  G06F30/398 ,  G06F30/394 ,  G06F30/327

Abstract: Various implementations described herein refer to a method. The method may be configured to synthesize standard cells for a physical design having a power supply net with power supply rails. The method may be configured to employ a place-and-route tool so as to define edge-types for each standard cell of the standard cells in the physical design based on the power supply net and the power supply rails that touch at least one edge of each standard cell of the standard cells.

公开(公告)号：US20220147679A1

公开(公告)日：2022-05-12

申请号：US17091229

申请日：2020-11-06

Applicant: Arm Limited

Inventor： Sharath Koodali Edathil ,  Marlin Wayne Frederick, JR.

IPC: G06F30/373 ,  G06F30/394 ,  G06F30/398 ,  G06F30/327

Abstract: Various implementations described herein refer to a method. The method may be configured to synthesize standard cells for a physical design having a power supply net with power supply rails. The method may be configured to employ a place-and-route tool so as to define edge-types for each standard cell of the standard cells in the physical design based on the power supply net and the power supply rails that touch at least one edge of each standard cell of the standard cells.

公开(公告)号：US12248743B2

公开(公告)日：2025-03-11

申请号：US17685166

申请日：2022-03-02

Applicant: Arm Limited

Inventor： Sharath Koodali Edathil ,  Marlin Wayne Frederick, Jr.

IPC: G06F30/398 ,  G06F30/327 ,  G06F30/373 ,  G06F30/394

Abstract: Various implementations described herein refer to a method. The method may be configured to synthesize standard cells for a physical design having a power supply net with power supply rails. The method may be configured to employ a place-and-route tool so as to define edge-types for each standard cell of the standard cells in the physical design based on the power supply net and the power supply rails that touch at least one edge of each standard cell of the standard cells.

公开(公告)号：US11967551B2

公开(公告)日：2024-04-23

申请号：US17224898

申请日：2021-04-07

Applicant: Arm Limited

Inventor： Ronald Paxton Preston ,  Sharath Koodali Edathil

IPC: H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L23/528

Abstract: Various implementations described herein are directed to a device having a switch structure having an input and an output. The device may have a first thru-silicon via that couples a first backside signal to the input of the switch structure. The device may have a second thru-silicon via that couples a second backside signal to the output of the switch structure.

公开(公告)号：US20220328399A1

公开(公告)日：2022-10-13

申请号：US17224898

申请日：2021-04-07

Applicant: Arm Limited

Inventor： Ronald Paxton Preston ,  Sharath Koodali Edathil

IPC: H01L23/522 ,  H01L23/528

Abstract: Various implementations described herein are directed to a device having a switch structure having an input and an output. The device may have a first thru-silicon via that couples a first backside signal to the input of the switch structure. The device may have a second thru-silicon via that couples a second backside signal to the output of the switch structure.