公开(公告)号：US11068639B2

公开(公告)日：2021-07-20

申请号：US16165675

申请日：2018-10-19

Applicant: Arm Limited

Inventor： Marlin Wayne Frederick, Jr. ,  Ettore Amirante ,  Ronald Paxton Preston ,  Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong

IPC: G06F30/39 ,  G06F30/394 ,  G11C11/419 ,  G11C7/12

Abstract: Various implementations described herein refer to a method. The method may include providing a metal layout for an integrated circuit, wherein the metal layout includes multiple lines associated with bitlines. The method may include inserting at least one additional line between the multiple lines and the bitlines. The method may include arranging the at least one additional line with respect to the multiple lines and the bitlines so as to reduce capacitance associated with the bitlines.

公开(公告)号：US20200286548A1

公开(公告)日：2020-09-10

申请号：US16294577

申请日：2019-03-06

Applicant: Arm Limited

Inventor： Marlin Wayne Frederick, JR. ,  Ronald Paxton Preston ,  Andy Wangkun Chen ,  Yew Keong Chong

IPC: G11C11/412 ,  G11C11/419

Abstract: Various implementations described herein refer to an integrated circuit having an array of bitcells coupled between at least one pair of bitlines including a first bitline and a second bitline that is a complement of the first bitline. The integrated circuit may include at least one pair of ancillary lines disposed adjacent to the at least one pair of bitlines, and the at least one pair of ancillary lines include a first ancillary line disposed adjacent to the first bitline and a second ancillary line disposed adjacent to the second bitline. The integrated circuit may include multiple pairs of passgates coupled between the at least one pair of bitlines and the at least one pair of ancillary lines.

公开(公告)号：US11967551B2

公开(公告)日：2024-04-23

申请号：US17224898

申请日：2021-04-07

Applicant: Arm Limited

Inventor： Ronald Paxton Preston ,  Sharath Koodali Edathil

IPC: H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L23/528

Abstract: Various implementations described herein are directed to a device having a switch structure having an input and an output. The device may have a first thru-silicon via that couples a first backside signal to the input of the switch structure. The device may have a second thru-silicon via that couples a second backside signal to the output of the switch structure.

公开(公告)号：US20220328399A1

公开(公告)日：2022-10-13

申请号：US17224898

申请日：2021-04-07

Applicant: Arm Limited

Inventor： Ronald Paxton Preston ,  Sharath Koodali Edathil

IPC: H01L23/522 ,  H01L23/528

Abstract: Various implementations described herein are directed to a device having a switch structure having an input and an output. The device may have a first thru-silicon via that couples a first backside signal to the input of the switch structure. The device may have a second thru-silicon via that couples a second backside signal to the output of the switch structure.

公开(公告)号：US11011222B2

公开(公告)日：2021-05-18

申请号：US16294577

申请日：2019-03-06

Applicant: Arm Limited

Inventor： Marlin Wayne Frederick, Jr. ,  Ronald Paxton Preston ,  Andy Wangkun Chen ,  Yew Keong Chong

IPC: G11C11/412 ,  G11C11/419

Abstract: Various implementations described herein refer to an integrated circuit having an array of bitcells coupled between at least one pair of bitlines including a first bitline and a second bitline that is a complement of the first bitline. The integrated circuit may include at least one pair of ancillary lines disposed adjacent to the at least one pair of bitlines, and the at least one pair of ancillary lines include a first ancillary line disposed adjacent to the first bitline and a second ancillary line disposed adjacent to the second bitline. The integrated circuit may include multiple pairs of passgates coupled between the at least one pair of bitlines and the at least one pair of ancillary lines.

公开(公告)号：US10083833B1

公开(公告)日：2018-09-25

申请号：US15629684

申请日：2017-06-21

Applicant: ARM Limited

Inventor： Ronald Paxton Preston ,  Marlin Wayne Frederick, Jr.

IPC: H01L21/033

CPC classification number: H01L21/0338 ,  G03F1/36 ,  G03F7/70441 ,  G06F17/5036 ,  G06F17/5068

Abstract: Various implementations described herein are directed to a method for manufacturing an integrated circuit. The method may include defining multiple lithographic regions for the integrated circuit, and the multiple lithographic regions may include a first lithographic region and a second lithographic region. The method may include defining an anchor in the first lithographic region and defining a target in the second lithographic region. The method may include defining a spacing interval between the anchor and the target. The method may include inserting an integration fill in the spacing interval.