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公开(公告)号：US11789701B2
公开(公告)日：2023-10-17
申请号：US16985447
申请日：2020-08-05
Applicant: Arm Limited
Inventor： Tai Li , Jack William Derek Andrew , Michael Alexander Kennedy
CPC classification number: G06F7/5443 , G06F7/5312
Abstract: A multiplier circuit is provided to multiply a first operand and a second operand. The multiplier circuit includes a carry-save adder network comprising a plurality of carry-save adders to perform partial product additions to reduce a plurality of partial products to a redundant result value that represents a product of the first operand and the second operand. A number of the carry-save adders that is used to generate the redundant result value is controllable and is dependent on a width of at least one of the first operand and the second operand.
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