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公开(公告)号：US11789701B2
公开(公告)日：2023-10-17
申请号：US16985447
申请日：2020-08-05
Applicant: Arm Limited
Inventor： Tai Li , Jack William Derek Andrew , Michael Alexander Kennedy
CPC classification number: G06F7/5443 , G06F7/5312
Abstract: A multiplier circuit is provided to multiply a first operand and a second operand. The multiplier circuit includes a carry-save adder network comprising a plurality of carry-save adders to perform partial product additions to reduce a plurality of partial products to a redundant result value that represents a product of the first operand and the second operand. A number of the carry-save adders that is used to generate the redundant result value is controllable and is dependent on a width of at least one of the first operand and the second operand.
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公开(公告)号：US11550735B1
公开(公告)日：2023-01-10
申请号：US17486639
申请日：2021-09-27
Applicant: Arm Limited
Inventor： François Christopher Jacques Botman , Thomas Christopher Grocutt , Jack William Derek Andrew
Abstract: Memory access control circuitry controls handling of a memory access request based on at least one memory access control attribute associated with a region of address space including the target address. The memory access control circuitry comprises: lookup circuitry comprising a plurality of sets of comparison circuitry, each set of comparison circuitry to detect, based on at least one address-region-indicating parameter associated with a corresponding region of address space, whether the target address is within the corresponding region of address space; region mismatch prediction circuitry to provide a region mismatch prediction indicative of which of the sets of comparison circuitry is predicted to detect a region mismatch condition; and comparison disabling circuitry to disable at least one of the sets of comparison circuitry that is predicted by the region mismatch prediction circuitry to detect the region mismatch condition for the target address.
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公开(公告)号：US11126691B1
公开(公告)日：2021-09-21
申请号：US16909147
申请日：2020-06-23
Applicant: Arm Limited
Inventor： Jack William Derek Andrew
Abstract: An apparatus is provided that receives a scalar start value, an adjust amount and wrapping control information, and includes vector generating circuitry for generating a vector comprising a plurality of elements such that a value of a first element is dependent on the scalar start value, and values of the plurality of elements follow a regularly progressing sequence that is constrained to wrap as required to ensure that each value is within bounds determined from the wrapping control information. The adjust amount is used to determine a difference between values of adjacent elements in the regularly progressing sequence. The vector generating circuitry has first adder circuitry for generating a plurality of first candidate values for the plurality of elements, assuming absence of a wrapping condition, and second adder circuitry for generating a plurality of second candidate values for the plurality of elements, assume presence of a wrapping condition. Wrap detection circuitry determines an adjustment limit value that provides an indication of a total number of regularly progressing values differing by the adjust amount that are available within the bounds determined from the wrapping control information, and a current adjustment value that, taking into account the scalar start value, provides an indication of an initial number of regularly progressing values differing by the adjust amount that are available before the wrapping condition occurs. Result selection circuitry selects, for each element in the plurality of elements, one of the first candidate values and the second candidate values, in dependence on at least the adjustment limit value and the current adjustment value.
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