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公开(公告)号：US11429426B2
公开(公告)日：2022-08-30
申请号：US17056896
申请日：2019-05-01
Applicant: Arm Limited
Abstract: An interrupt controller comprises issue circuitry to issue interrupt requests to a processing element and control circuitry to detect presence of a race condition in association with at least one pending interrupt request to be issued, and to set a barrier indicator when the race condition has been resolved. In response to the race condition being present, the issue circuitry is configured to select one of the at least one pending interrupt requests, to issue to the processing element the selected pending interrupt request followed by a dummy request over a path that ensures that the processing element receives the selected pending interrupt request prior to receiving the dummy request. On receiving an acknowledgement indicating that the processing element has received the dummy request, the control circuitry is then configured to set the barrier indicator.
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公开(公告)号：US09043522B2
公开(公告)日：2015-05-26
申请号：US13653472
申请日：2012-10-17
Applicant: ARM LIMITED
Inventor： Michael Alexander Kennedy , Anthony Jebson
CPC classification number: G06F13/24 , G06F9/4812 , G06F9/5027
Abstract: A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request.
Abstract translation: 数据处理装置具有多个处理器和多个中断接口，每个中断接口用于处理来自相应处理器的中断请求。 中断分配器控制中断请求到中断接口的路由。 共享中断请求可由多个处理器使用。 响应于共享中断请求，目标中断接口向中断分配器发出中断所有权请求，如果它估计相应的处理器可用于维护共享中断请求，则不会将共享中断请求传递给相应的处理器。 当从中断分配器接收到所有权确认，指示处理器被选择用于维护共享中断请求时，共享中断请求被传递给相应的处理器。
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公开(公告)号：US11068238B2
公开(公告)日：2021-07-20
申请号：US16417866
申请日：2019-05-21
Applicant: Arm Limited
Abstract: A multiplier circuit is described in which sub-products calculated in a first stage of a carry-save adder (CSA) network are output early, processed by applying a processing function, and re-injected into a subsequent stage of the CSA network to add the processed sub-products. This allows a CSA network provided for multiplication operations to be reused for operations which require sub-products to be processed and added, such as floating-point dot product operations performed on floating-point values represented in bfloatl6 format.
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公开(公告)号：US09430421B2
公开(公告)日：2016-08-30
申请号：US14206236
申请日：2014-03-12
Applicant: ARM Limited
CPC classification number: G06F13/26
Abstract: An interrupt controller includes a priority level arbitrator (8) including multiple stages. The stages include at least one stage comprising a plurality of interrupt selectors formed of a multiplexer (14) for selecting between a pair of potentially concurrently asserted interrupt signals in dependence upon selection data. The selection data is determined in advance by a priority level comparator (12) using priority level data associated with the respective interrupt signals.
Abstract translation: 中断控制器包括包括多个级的优先级仲裁器（8）。 这些级包括至少一个级，包括由多路复用器（14）形成的多个中断选择器，用于根据选择数据在一对潜在同时断言的中断信号之间进行选择。 优先级比较器（12）使用与各个中断信号相关联的优先级数据预先确定选择数据。
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公开(公告)号：US10019394B2
公开(公告)日：2018-07-10
申请号：US15464892
申请日：2017-03-21
Applicant: ARM Limited
Inventor： Michael Alexander Kennedy , Anthony Jebson
CPC classification number: G06F13/24 , G06F9/4812 , G06F9/5027
Abstract: A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request.
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Patent Agency Ranking
公开(公告)号：US09632957B2
公开(公告)日：2017-04-25
申请号：US14695325
申请日：2015-04-24
Applicant: ARM Limited
Inventor： Michael Alexander Kennedy , Anthony Jebson
CPC classification number: G06F13/24 , G06F9/4812 , G06F9/5027
Abstract: A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request.
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公开(公告)号：US20150261700A1
公开(公告)日：2015-09-17
申请号：US14206236
申请日：2014-03-12
Applicant: ARM Limited
IPC: G06F13/26
CPC classification number: G06F13/26
Abstract: An interrupt controller includes a priority level arbitrator (8) including multiple stages. The stages include at least one stage comprising a plurality of interrupt selectors formed of a multiplexer (14) for selecting between a pair of potentially concurrently asserted interrupt signals in dependence upon selection data. The selection data is determined in advance by a priority level comparator (12) using priority level data associated with the respective interrupt signals.
Abstract translation: 中断控制器包括包括多个级的优先级仲裁器（8）。 这些级包括至少一个级，包括由多路复用器（14）形成的多个中断选择器，用于根据选择数据在一对潜在同时断言的中断信号之间进行选择。 优先级比较器（12）使用与各个中断信号相关联的优先级数据预先确定选择数据。
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公开(公告)号：US20250028530A1
公开(公告)日：2025-01-23
申请号：US18711220
申请日：2022-10-18
Applicant: Arm Limited
Inventor： Mbou Eyole , Michael Alexander Kennedy , Giacomo Gabrielli
Abstract: There is provided a processing apparatus comprising decoder circuitry. The decoder circuitry is configured to generate control signals in response to an instruction. The processing apparatus further comprises processing circuitry which comprising a plurality of processing lanes. The processing circuitry is configured, in response to the control signals, to perform a vector processing operation in each processing lane of the plurality of processing lanes for which a per-lane mask indicates that processing for that processing lane is enabled. The processing apparatus further comprises control circuitry to monitor each processing lane of the plurality of processing lanes for each instruction of a plurality of instructions performed in the plurality of processing lanes and to modify the per-lane mask for a processing lane of the plurality of processing lanes in response to a processing state of the processing lane meeting one or more predetermined conditions.
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公开(公告)号：US11789701B2
公开(公告)日：2023-10-17
申请号：US16985447
申请日：2020-08-05
Applicant: Arm Limited
Inventor： Tai Li , Jack William Derek Andrew , Michael Alexander Kennedy
CPC classification number: G06F7/5443 , G06F7/5312
Abstract: A multiplier circuit is provided to multiply a first operand and a second operand. The multiplier circuit includes a carry-save adder network comprising a plurality of carry-save adders to perform partial product additions to reduce a plurality of partial products to a redundant result value that represents a product of the first operand and the second operand. A number of the carry-save adders that is used to generate the redundant result value is controllable and is dependent on a width of at least one of the first operand and the second operand.
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公开(公告)号：US10409604B2
公开(公告)日：2019-09-10
申请号：US15859931
申请日：2018-01-02
Applicant: Arm Limited
Inventor： Michael Alexander Kennedy , Neil Burgess
Abstract: An apparatus and method are provided for performing multiply-and-accumulate-products (MAP) operations. The apparatus has processing circuitry for performing data processing, the processing circuitry including an adder array having a plurality of adders for accumulating partial products produced from input operands. An instruction decoder is provided that is responsive to a MAP instruction specifying a first J-bit operand and a second K-bit operand, to control the processing circuitry to enable performance of a number of MAP operations, where the number is dependent on a parameter. For each performed MAP operation, the processing circuitry is arranged to generate a corresponding result element representing a sum of respective E×F products of E-bit portions within an X-bit segment of the first operand with F-bit portions within a Y-bit segment of the second operand, where E
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