公开(公告)号：US10445241B2

公开(公告)日：2019-10-15

申请号：US15912659

申请日：2018-03-06

Applicant: Arm Limited

Inventor： Lucas Garcia ,  Laurent Claude Desnogues ,  Adrien Pesle ,  Vincenzo Consales

IPC: G06F12/08 ,  G06F12/0862

Abstract: Data processing circuitry comprises a processing element to execute successive iterations of program code to access a set of data elements in memory, each iteration accessing one or more respective data elements of the set; a data element structure memory to store a memory address relationship between the data elements of the set; and prefetch circuitry, responsive to an access by a current program code iteration to a current data element of the set, to detect, using the memory address relationship stored in the data element structure memory a memory address defining a subsequent data element to be accessed by a next program iteration and to initiate prefetching of at least a portion of the subsequent data element from memory.

公开(公告)号：US10691461B2

公开(公告)日：2020-06-23

申请号：US15852065

申请日：2017-12-22

Applicant: Arm Limited

Inventor： Houdhaifa Bouzguarrou ,  Guillaume Bolbenes ,  Vincenzo Consales ,  Eddy Lapeyre

IPC: G06F9/38 ,  G06F9/30

Abstract: Data processing circuitry comprises fetch circuitry to fetch blocks, containing instructions for execution, defined by a fetch queue; and prediction circuitry to predict one or more next blocks to be fetched and to add the predicted next blocks to the fetch queue; the prediction circuitry comprising: branch prediction circuitry to detect a predicted branch destination for a branch instruction in a current block, the predicted branch destination representing either a branch target for a branch predicted to be taken or a next instruction after the branch instruction, for a branch predicted not to be taken; and sequence prediction circuitry to detect sequence data, associated with the predicted branch destination, identifying a next block following the predicted branch destination in the program flow order having a next instance of a branch instruction, to add to the fetch queue the identified next block and any intervening blocks between the current block and the identified next block, and to initiate branch prediction in respect of the predicted next instance of a branch instruction.

公开(公告)号：US11226824B2

公开(公告)日：2022-01-18

申请号：US16656877

申请日：2019-10-18

Applicant: Arm Limited

Inventor： Houdhaifa Bouzguarrou ,  Vincenzo Consales

IPC: G06F9/38 ,  G06F21/75 ,  G06F9/30 ,  G06F3/06

Abstract: Circuitry comprises a prediction register storing a plurality of entries each having respective data values for association with one or more branch instructions; prediction circuitry to detect, using prediction data derived by a mapping function from the stored data values associated with a given branch instruction, whether or not a branch represented by the given branch instruction is predicted to be taken; update circuitry to modify the stored data values associated with the given branch instruction in dependence upon a resolution of whether the branch represented by the given branch instruction is taken or not; and control circuitry configured to selectively alter one or more of the data values other than data values associated with the given branch instruction.

公开(公告)号：US11709782B2

公开(公告)日：2023-07-25

申请号：US17512888

申请日：2021-10-28

Applicant: Arm Limited

Inventor： Paolo Monti ,  Abdel Hadi Moustafa ,  Albin Pierrick Tonnerre ,  Vincenzo Consales ,  Abhishek Raja

IPC: G06F12/10 ,  G06F12/1027

CPC classification number: G06F12/1027 ,  G06F2212/68

Abstract: Circuitry comprises a translation lookaside buffer to store memory address translations, each memory address translation being between an input memory address range defining a contiguous range of one or more input memory addresses in an input memory address space and a translated output memory address range defining a contiguous range of one or more output memory addresses in an output memory address space; in which the translation lookaside buffer is configured selectively to store the memory address translations as a cluster of memory address translations, a cluster defining memory address translations in respect of a contiguous set of input memory address ranges by encoding one or more memory address offsets relative to a respective base memory address; memory management circuitry to retrieve data representing memory address translations from a memory, for storage by the translation lookaside buffer, when a required memory address translation is not stored by the translation lookaside buffer; detector circuitry to detect an action consistent with access, by the translation lookaside buffer, to a given cluster of memory address translations; and prefetch circuitry, responsive to a detection of the action consistent with access to a cluster of memory address translations, to prefetch data from the memory representing one or more further memory address translations of a further set of input memory address ranges adjacent to the contiguous set of input memory address ranges for which the given cluster defines memory address translations.

公开(公告)号：US11281467B2

公开(公告)日：2022-03-22

申请号：US16654372

申请日：2019-10-16

Applicant: Arm Limited

Inventor： Houdhaifa Bouzguarrou ,  Guillaume Bolbenes ,  Vincenzo Consales

IPC: G06F9/38 ,  G06F9/30

Abstract: Circuitry comprises a prediction register having one or more entries each storing prediction data; prediction circuitry configured to map a value of the stored prediction data to a prediction of whether or not a branch represented by a given branch instruction is predicted to be taken, according to a data mapping; and control circuitry configured to selectively vary the data mapping between the prediction and the value of the stored prediction data.