公开(公告)号：US10896707B2

公开(公告)日：2021-01-19

申请号：US16290822

申请日：2019-03-01

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Rahul Mathur ,  Cyrille Nicolas Dray ,  Yann Sarrazin ,  Julien Vincent Poitrat ,  Yannis Jallamion-Grive ,  Pranay Prabhat ,  James Edward Myers ,  Graham Peter Knight ,  Jonas {hacek over (S)}vedas

IPC: G11C8/00 ,  G11C11/00 ,  G11C11/16

Abstract: Briefly, embodiments of claimed subject matter relate to adjusting, such as extending, a clock signal to permit completion of a write operations to a first memory type and/or to permit completion of read operations from a second memory type, wherein the first memory type and the second memory type are dissimilar from each other. In certain embodiments, the first memory type may comprise a magnetic random-access memory (MRAM) cell array, and the second memory type may comprise a static random-access memory (SRAM) cell array.