公开(公告)号：US10896707B2

公开(公告)日：2021-01-19

申请号：US16290822

申请日：2019-03-01

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Rahul Mathur ,  Cyrille Nicolas Dray ,  Yann Sarrazin ,  Julien Vincent Poitrat ,  Yannis Jallamion-Grive ,  Pranay Prabhat ,  James Edward Myers ,  Graham Peter Knight ,  Jonas {hacek over (S)}vedas

IPC: G11C8/00 ,  G11C11/00 ,  G11C11/16

Abstract: Briefly, embodiments of claimed subject matter relate to adjusting, such as extending, a clock signal to permit completion of a write operations to a first memory type and/or to permit completion of read operations from a second memory type, wherein the first memory type and the second memory type are dissimilar from each other. In certain embodiments, the first memory type may comprise a magnetic random-access memory (MRAM) cell array, and the second memory type may comprise a static random-access memory (SRAM) cell array.

公开(公告)号：US10886847B1

公开(公告)日：2021-01-05

申请号：US16441228

申请日：2019-06-14

Applicant: Arm Limited

Inventor： Benoit Labbe ,  Graham Peter Knight ,  Philex Ming-Yan Fan

IPC: H02M3/157 ,  G04F10/00 ,  H02M3/158 ,  H02M1/00

Abstract: Various implementations described herein are directed to a device having a voltage regulator that uses a modulator to adjust an output voltage. The device may include a time-to-digital converter that measures a timing delay of a logic chain, compares the timing delay to a reference delay to determine a timing delay error, and provides the timing delay error to the modulator for adjusting the output voltage.

公开(公告)号：US11200940B2

公开(公告)日：2021-12-14

申请号：US16683192

申请日：2019-11-13

Applicant: Arm Limited

Inventor： Pranay Prabhat ,  James Edward Myers ,  Graham Peter Knight

IPC: G11C7/02 ,  G11C11/4072 ,  G11C11/408 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4094

Abstract: According to one implementation of the present disclosure, a memory array to block read-access of uninitialized memory locations is disclosed. The memory array includes: a plurality of memory cells apportioned into a plurality of memory columns and a plurality of memory rows, where each of the memory cells is configured to store a single bit of memory data; and one or more initialization columns corresponding to at least one of the plurality of memory columns. The initialization state of a memory row of the memory cells may be configured to be stored in: the memory row; a latch of word-line driver circuitry coupled to the memory array; or a memory cell of the one or more initialization columns of a corresponding row of the plurality of memory rows of the memory array.

公开(公告)号：US20210142839A1

公开(公告)日：2021-05-13

申请号：US16683192

申请日：2019-11-13

Applicant: Arm Limited

Inventor： Pranay Prabhat ,  James Edward Myers ,  Graham Peter Knight

IPC: G11C11/4072 ,  G11C11/408 ,  G11C11/4094 ,  G11C7/22 ,  G11C7/10

Abstract: According to one implementation of the present disclosure, a memory array to block read-access of uninitialized memory locations is disclosed. The memory array includes: a plurality of memory cells apportioned into a plurality of memory columns and a plurality of memory rows, where each of the memory cells is configured to store a single bit of memory data; and one or more initialization columns corresponding to at least one of the plurality of memory columns. The initialization state of a memory row of the memory cells may be configured to be stored in: the memory row; a latch of word-line driver circuitry coupled to the memory array; or a memory cell of the one or more initialization columns of a corresponding row of the plurality of memory rows of the memory array.