公开(公告)号：US20090216955A1

公开(公告)日：2009-08-27

申请号：US12035906

申请日：2008-02-22

申请人： Arthur J. O'Neill, JR. ,  Michael F. Fee ,  Pak-kin Mak

发明人： Arthur J. O'Neill, JR. ,  Michael F. Fee ,  Pak-kin Mak

IPC分类号： G06F12/00

CPC分类号： G06F12/123 ,  G06F12/0859

摘要： A two pipe pass method for least recently used (LRU) compartment capture in a multiprocessor system. The method includes receiving a fetch request via a requesting processor and accessing a cache directory based on the received fetch request, performing a first pipe pass by determining whether a fetch hit or a fetch miss has occurred in the cache directory, and determining an LRU compartment associated with a specified congruence class of the cache directory based on the fetch request received, when it is determined that a fetch miss has occurred, and performing a second pipe pass by using the LRU compartment determined and the specified congruence class to access the cache directory and to select an LRU address to be cast out of the cache directory.

摘要翻译： 在多处理器系统中用于最近最少使用（LRU）隔室捕获的两个管道通过方法。 该方法包括：通过请求处理器接收提取请求，并基于接收的提取请求访问高速缓存目录;通过确定高速缓存目录中是否发生了提取命中或提取丢失，执行第一管道通路，以及确定LRU隔间 当确定已经发生提取未命中时，基于所接收的获取请求与缓存目录的指定同余类相关联，并且通过使用确定的LRU隔离区和指定的一致等级来访问高速缓存目录来执行第二管道传递 并选择要从缓存目录中抛出的LRU地址。

公开(公告)号：US08180970B2

公开(公告)日：2012-05-15

申请号：US12035906

申请日：2008-02-22

申请人： Arthur J. O'Neill, Jr. ,  Michael F. Fee ,  Pak-kin Mak

发明人： Arthur J. O'Neill, Jr. ,  Michael F. Fee ,  Pak-kin Mak

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/123 ,  G06F12/0859

摘要： A two pipe pass method for least recently used (LRU) compartment capture in a multiprocessor system. The method includes receiving a fetch request via a requesting processor and accessing a cache directory based on the received fetch request, performing a first pipe pass by determining whether a fetch hit or a fetch miss has occurred in the cache directory, and determining an LRU compartment associated with a specified congruence class of the cache directory based on the fetch request received, when it is determined that a fetch miss has occurred, and performing a second pipe pass by using the LRU compartment determined and the specified congruence class to access the cache directory and to select an LRU address to be cast out of the cache directory.

摘要翻译： 在多处理器系统中用于最近最少使用（LRU）隔室捕获的两个管道通过方法。 该方法包括：通过请求处理器接收提取请求，并基于接收的提取请求访问高速缓存目录;通过确定高速缓存目录中是否发生了提取命中或提取丢失，执行第一管道通路，以及确定LRU隔间 当确定已经发生提取未命中时，基于所接收的获取请求与缓存目录的指定同余类相关联，并且通过使用确定的LRU隔离区和指定的一致等级来访问高速缓存目录来执行第二管道传递 并选择要从缓存目录中抛出的LRU地址。

公开(公告)号：US20090210629A1

公开(公告)日：2009-08-20

申请号：US12032058

申请日：2008-02-15

申请人： Michael A. Blake ,  Christine C. Jones ,  Pak-kin Mak ,  Arthur J. O'Neill, JR.

发明人： Michael A. Blake ,  Christine C. Jones ,  Pak-kin Mak ,  Arthur J. O'Neill, JR.

IPC分类号： G06F12/08

CPC分类号： G06F12/0817

摘要： A method, system and computer program product for selectively purging entries in a cache of a computer system. The method includes determining a starting storage address and a length of the storage address range to be purged, determining preset values for a congruence class and a compartment of a cache directory, accessing the cache directory based on the preset value of the congruence class, and selecting an entry in the cache directory based on the preset value of the compartment, determining validity of the entry accessed by examining an ownership tag of the entry, comparing a line address of the entry with the starting storage address and a sum of the starting storage address and the length of the storage address range, and selectively purging the entry based on the comparison result.

摘要翻译： 一种用于选择性地清除计算机系统的高速缓存中的条目的方法，系统和计算机程序产品。 该方法包括确定要清除的存储地址范围的起始存储地址和长度，确定高速缓存目录的同余类和隔间的预设值，基于同余类的预设值访问高速缓存目录;以及 基于所述隔室的所述预设值来选择所述缓存目录中的条目，通过检查所述条目的所有权标签来确定所访问的条目的有效性，将所述条目的行地址与所述起始存储地址进行比较，以及所述起始存储器 地址和存储地址范围的长度，并且基于比较结果选择性地清除条目。

公开(公告)号：US08250308B2

公开(公告)日：2012-08-21

申请号：US12031977

申请日：2008-02-15

申请人： Vesselina K. Papazova ,  Ekaterina M. Ambroladze ,  Michael A. Blake ,  Pak-kin Mak ,  Arthur J. O'Neill, Jr. ,  Craig R. Waters

发明人： Vesselina K. Papazova ,  Ekaterina M. Ambroladze ,  Michael A. Blake ,  Pak-kin Mak ,  Arthur J. O'Neill, Jr. ,  Craig R. Waters

IPC分类号： G06F12/00

CPC分类号： G06F12/0831

摘要： The method includes initiating a processor request to a cache in a requesting node and broadcasting the processor request to remote nodes when the processor request encounters a local cache miss, performing a directory search of each remote cache to determine a state of a target line's address and an ownership state of a specified address, returning the state of the target line to the requesting node and forming a combined response, and broadcasting the combined response to each remote node. During a fetch operation, when the directory search indicates an IM or a Target Memory node on a remote node, data is sourced from the respective remote cache and forwarded to the requesting node while protecting the data, and during a store operation, the data is sourced from the requesting node and protected while being forwarded to the IM or the Target Memory node after coherency has been established.

摘要翻译： 该方法包括：当处理器请求遇到本地高速缓存未命中时，向请求节点中的高速缓存发起处理器请求并将处理器请求广播到远程节点，执行每个远程高速缓存的目录搜索以确定目标行的地址的状态，以及 指定地址的所有权状态，将目标行的状态返回到请求节点并形成组合响应，并将组合的响应广播到每个远程节点。 在获取操作期间，当目录搜索指示远程节点上的IM或目标存储器节点时，数据来自相应的远程高速缓存并且在保护数据的同时被转发到请求节点，并且在存储操作期间，数据是 源自请求节点，并且在一致性被建立之后被转发到IM或目标存储器节点时被保护。

公开(公告)号：US07934059B2

公开(公告)日：2011-04-26

申请号：US12021781

申请日：2008-01-29

申请人： Vesselina K. Papazova ,  Michael A. Blake ,  Pak-kin Mak ,  Arthur J. O'Neill, Jr. ,  Craig R. Waters

发明人： Vesselina K. Papazova ,  Michael A. Blake ,  Pak-kin Mak ,  Arthur J. O'Neill, Jr. ,  Craig R. Waters

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F2212/507

摘要： A method of preventing lockout and stalling conditions in a multi-node system having a plurality of nodes which includes initiating a processor request to a shared level of cache in a requesting node, performing a fabric coherency establishment sequence on the plurality of nodes, issuing a speculative memory fetch request to a memory, detecting a conflict on one of the plurality of nodes and communicating the conflict back to the requesting node within the system, canceling the speculative memory fetch request issued, and repeating the fabric coherency establishment sequence in the system until the point of conflict is resolved, without issuing another speculative memory fetch request. The subsequent memory fetch request is only issued after determining the state of line within the system, after the successful completion of the multi-node fabric coherency establishment sequence.

摘要翻译： 一种在具有多个节点的多节点系统中防止锁定和停顿状态的方法，包括：向请求节点中的高速缓存的共享级别发起处理器请求，在所述多个节点上执行结构一致性建立序列，发出 对存储器的推测性存储器提取请求，检测多个节点中的一个节点上的冲突并将冲突传送回系统内的请求节点，取消发出的推测性存储器提取请求，并重复系统中的结构一致性建立序列，直到 解决冲突的点，而不发出另一个推测性的内存提取请求。 随后的内存提取请求仅在确定多节点结构一致性建立序列成功完成后确定系统中的线路状态之后发出。

公开(公告)号：US20090193198A1

公开(公告)日：2009-07-30

申请号：US12021781

申请日：2008-01-29

申请人： Vesselina K. Papazova ,  Michael A. Blake ,  Pak-kin Mak ,  Arthur J. O'Neill, Jr. ,  Craig R. Waters

发明人： Vesselina K. Papazova ,  Michael A. Blake ,  Pak-kin Mak ,  Arthur J. O'Neill, Jr. ,  Craig R. Waters

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F2212/507

摘要： A method of preventing lockout and stalling conditions in a multi-node system having a plurality of nodes which includes initiating a processor request to a shared level of cache in a requesting node, performing a fabric coherency establishment sequence on the plurality of nodes, issuing a speculative memory fetch request to a memory, detecting a conflict on one of the plurality of nodes and communicating the conflict back to the requesting node within the system, canceling the speculative memory fetch request issued, and repeating the fabric coherency establishment sequence in the system until the point of conflict is resolved, without issuing another speculative memory fetch request. The subsequent memory fetch request is only issued after determining the state of line within the system, after the successful completion of the multi-node fabric coherency establishment sequence.

摘要翻译： 一种在具有多个节点的多节点系统中防止锁定和停顿状态的方法，包括：向请求节点中的高速缓存的共享级别发起处理器请求，在所述多个节点上执行结构一致性建立序列，发出 对存储器的推测性存储器提取请求，检测多个节点中的一个节点上的冲突并将冲突传送回系统内的请求节点，取消发出的推测性存储器提取请求，并重复系统中的结构一致性建立序列，直到 解决冲突的点，而不发出另一个推测性的内存提取请求。 随后的内存提取请求仅在确定多节点结构一致性建立序列成功完成后确定系统中的线路状态之后发出。

公开(公告)号：US20090210626A1

公开(公告)日：2009-08-20

申请号：US12031977

申请日：2008-02-15

申请人： Vesselina K. Papazova ,  Ekaterina M. Ambroladze ,  Michael A. Blake ,  Pak-kin Mak ,  Arthur J. O'Neill, JR. ,  Craig R. Waters

发明人： Vesselina K. Papazova ,  Ekaterina M. Ambroladze ,  Michael A. Blake ,  Pak-kin Mak ,  Arthur J. O'Neill, JR. ,  Craig R. Waters

IPC分类号： G06F12/00

CPC分类号： G06F12/0831

摘要： The method includes initiating a processor request to a cache in a requesting node and broadcasting the processor request to remote nodes when the processor request encounters a local cache miss, performing a directory search of each remote cache to determine a state of a target line's address and an ownership slate of a specified address, returning the state of the target line to the requesting node and forming a combined response, and broadcasting the combined response to each remote node. During a fetch operation, when the directory search indicates an IM or a Target Memory node on a remote node, data is sourced from the respective remote cache and forwarded to the requesting node while protecting the data, and during a store operation, the data is sourced from the requesting node and protected while being forwarded to the IM or the Target Memory node after coherency has been established.

摘要翻译： 该方法包括：当处理器请求遇到本地高速缓存未命中时，向请求节点中的高速缓存发起处理器请求并将处理器请求广播到远程节点，执行每个远程高速缓存的目录搜索以确定目标行的地址的状态，以及 指定地址的所有权，将目标行的状态返回到请求节点并形成组合的响应，并将组合的响应广播到每个远程节点。 在获取操作期间，当目录搜索指示远程节点上的IM或目标存储器节点时，数据来自相应的远程高速缓存并且在保护数据的同时被转发到请求节点，并且在存储操作期间，数据是 源自请求节点，并且在一致性被建立之后被转发到IM或目标存储器节点时被保护。

公开(公告)号：US08250305B2

公开(公告)日：2012-08-21

申请号：US12051244

申请日：2008-03-19

申请人： Gary E. Strait ,  Deanna P. Dunn ,  Michael F. Fee ,  Pak-kin Mak ,  Robert J. Sonnelitter, III

发明人： Gary E. Strait ,  Deanna P. Dunn ,  Michael F. Fee ,  Pak-kin Mak ,  Robert J. Sonnelitter, III

IPC分类号： G06F13/00 ,  G06F13/28

CPC分类号： G06F12/126 ,  G06F2212/2515

摘要： Systems, methods and computer program products for data buffers partitioned from a cache array. An exemplary embodiment includes a method in a processor and for providing data buffers partitioned from a cache array, the method including clearing cache directories associated with the processor to an initial state, obtaining a selected directory state from a control register preloaded by the service processor, in response to the control register including the desired cache state, sending load commands with an address and data, loading cache lines and cache line directory entries into the cache and storing the specified data in the corresponding cache line.

摘要翻译： 从缓存阵列分区的数据缓冲区的系统，方法和计算机程序产品。 示例性实施例包括处理器中的方法并且用于提供从高速缓存阵列分区的数据缓冲器，该方法包括将与处理器相关联的高速缓存目录清除到初始状态，从由服务处理器预加载的控制寄存器获得所选择的目录状态， 响应于包括所需缓存状态的控制寄存器，发送具有地址和数据的加载命令，将高速缓存行和高速缓存行目录条目加载到高速缓存中并将指定的数据存储在相应的高速缓存行中。

公开(公告)号：US20110320755A1

公开(公告)日：2011-12-29

申请号：US12821986

申请日：2010-06-23

申请人： Michael A. Blake ,  Pak-kin Mak ,  Michael F. Fee ,  Mark S. Farrell

发明人： Michael A. Blake ,  Pak-kin Mak ,  Michael F. Fee ,  Mark S. Farrell

IPC分类号： G06F12/06

CPC分类号： G06F12/0292

摘要： Tracking dynamic memory de-allocation using a single configuration table having a first register and a second register includes setting the first register as an active register, initiating a de-allocation of desired storage increments from a memory partition, setting the storage increments in the second register as invalid, purging all caches associated with the single configuration table, setting the second register as the active register and the first register as an inactive register, setting the desired storage increments in the first register as invalid, switching the active register from the second register to the first register to complete memory de-allocation using the single configuration table.

摘要翻译： 使用具有第一寄存器和第二寄存器的单个配置表来跟踪动态存储器去分配包括将第一寄存器设置为活动寄存器，启动从存储器分区的期望存储增量的去分配，在第二寄存器中设置存储增量 注册为无效，清除与单个配置表相关联的所有高速缓存，将第二个寄存器设置为活动寄存器，将第一个寄存器设置为非活动寄存器，将第一个寄存器中的所需存储增量设置为无效，将活动寄存器从第二个 注册到第一个寄存器，使用单个配置表完成内存取消分配。

公开(公告)号：US08645642B2

公开(公告)日：2014-02-04

申请号：US12821986

申请日：2010-06-23

申请人： Michael A. Blake ,  Pak-kin Mak ,  Michael F. Fee ,  Mark S. Farrell

发明人： Michael A. Blake ,  Pak-kin Mak ,  Michael F. Fee ,  Mark S. Farrell

IPC分类号： G06F12/00

CPC分类号： G06F12/0292

摘要： Tracking dynamic memory de-allocation using a single configuration table having a first register and a second register includes setting the first register as an active register, initiating a de-allocation of desired storage increments from a memory partition, setting the storage increments in the second register as invalid, purging all caches associated with the single configuration table, setting the second register as the active register and the first register as an inactive register, setting the desired storage increments in the first register as invalid, switching the active register from the second register to the first register to complete memory de-allocation using the single configuration table.

摘要翻译： 使用具有第一寄存器和第二寄存器的单个配置表来跟踪动态存储器去分配包括将第一寄存器设置为活动寄存器，启动从存储器分区的期望存储增量的去分配，在第二寄存器中设置存储增量 注册为无效，清除与单个配置表相关联的所有高速缓存，将第二个寄存器设置为活动寄存器，将第一个寄存器设置为非活动寄存器，将第一个寄存器中的所需存储增量设置为无效，将活动寄存器从第二个 注册到第一个寄存器，使用单个配置表完成内存取消分配。