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    Architecture for power of two coefficient FIR filter
    1.
    发明授权
    Architecture for power of two coefficient FIR filter 失效
    两系数FIR滤波器的功率结构

    公开(公告)号：US4782458A

    公开(公告)日：1988-11-01

    申请号：US944295

    申请日：1986-12-18

    申请人： Arup K. Bhattacharya ,  Michael G. Cristofalo ,  David Koo ,  Amihai Miron ,  Imran A. Shah

    发明人： Arup K. Bhattacharya ,  Michael G. Cristofalo ,  David Koo ,  Amihai Miron ,  Imran A. Shah

    IPC分类号： G06F17/15 ,  H03H17/02 ,  H03H17/06 ,  G06F15/31

    CPC分类号： H03H17/06 ,  G06F17/15 ,  H03H17/0227 ,  H03H2017/0232

    摘要： An architecture for a very large scale integrated (VLSI) implementation of a finite imprise response (FIR) digital filter having no multipliers and a coefficient space limited to powers of two. The filter structure includes a data bus, a coefficient bus and a sum-in bus to each coefficient tap. Each tap has a coefficient and control word register which is loaded during an initialization phase of the filter. Multiplication is provided by a shifter which provides the correct power of two weighting of an input data sample. The weighted data sample at each tap is added to the output of the previous tap. This architecture results in a regular, modular structure which can be cascaded and which is programmable for various data word lengths and coefficient spaces.

    摘要翻译： 一种用于大规模集成（VLSI）实现的有限扩展响应（FIR）数字滤波器的架构，其没有乘法器和限制为2的幂的系数空间。 滤波器结构包括数据总线，系数总线和到每个系数抽头的总和总线。 每个抽头具有系数和控制字寄存器，它在滤波器的初始化阶段加载。 乘法由提供输入数据样本的两个加权的正确功率的移位器提供。 每个水龙头的加权数据样本将添加到先前水龙头的输出。 该架构产生了可以级联的规则的模块化结构，并且可针对各种数据字长度和系数空间进行编程。