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公开(公告)号：US4782458A
公开(公告)日：1988-11-01
申请号：US944295
申请日：1986-12-18
CPC分类号： H03H17/06 , G06F17/15 , H03H17/0227 , H03H2017/0232
摘要： An architecture for a very large scale integrated (VLSI) implementation of a finite imprise response (FIR) digital filter having no multipliers and a coefficient space limited to powers of two. The filter structure includes a data bus, a coefficient bus and a sum-in bus to each coefficient tap. Each tap has a coefficient and control word register which is loaded during an initialization phase of the filter. Multiplication is provided by a shifter which provides the correct power of two weighting of an input data sample. The weighted data sample at each tap is added to the output of the previous tap. This architecture results in a regular, modular structure which can be cascaded and which is programmable for various data word lengths and coefficient spaces.
摘要翻译： 一种用于大规模集成（VLSI）实现的有限扩展响应（FIR）数字滤波器的架构，其没有乘法器和限制为2的幂的系数空间。 滤波器结构包括数据总线，系数总线和到每个系数抽头的总和总线。 每个抽头具有系数和控制字寄存器，它在滤波器的初始化阶段加载。 乘法由提供输入数据样本的两个加权的正确功率的移位器提供。 每个水龙头的加权数据样本将添加到先前水龙头的输出。 该架构产生了可以级联的规则的模块化结构，并且可针对各种数据字长度和系数空间进行编程。
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2.发明授权
公开(公告)号：US4791597A
公开(公告)日：1988-12-13
申请号：US923534
申请日：1986-10-27
申请人： Amihai Miron , David Koo
发明人： Amihai Miron , David Koo
CPC分类号： H03H17/06 , G06F17/15 , H03H17/0227
摘要： A multiplierless digital FIR filter comprising a plurality of serially cascaded stages providing a non-linear series of two to the Nth power coefficient values, and in which quantization error is reduced by scaling the coefficient values to minimize root mean square error. Each stage includes a basic unit and an incremental unit, the basic unit providing two shift operations and including a delay element and an adder. To achieve a particular quantization error, one or more incremental units are connected in series with the basic unit in each stage, each such incremental unit providing a single shift operation and including a delay element and an adder. The number of incremental units in each stage and the number of cascaded stages can be selected to achieve a filter having desired performance characteristics and which can be realized on a VLSI chip.
摘要翻译： 一种无乘数数字FIR滤波器，包括多个串联级联级，提供两个到第N个功率系数值的非线性系列，并且通过缩放系数值来减小量化误差以使均方根误差最小化。 每个级包括基本单元和增量单元，基本单元提供两个移位操作并且包括延迟元件和加法器。 为了实现特定的量化误差，在每个级中一个或多个增量单元与基本单元串联连接，每个这样的增量单元提供单个移位操作并且包括延迟元件和加法器。 可以选择每个级中的增量单元数量和级联级数来实现具有期望性能特性并且可以在VLSI芯片上实现的滤波器。
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公开(公告)号：US4665438A
公开(公告)日：1987-05-12
申请号：US816026
申请日：1986-01-03
申请人： Amihai Miron , David Koo
发明人： Amihai Miron , David Koo
CPC分类号： H04N9/641
摘要： A color television receiver, having a tuner and associated demodulation circuits for both a main picture signal and a picture-in-picture (PIP) signal, uses a single memory for synchronization and for storing a single subsampled field of the PIP signal. Appropriate circuitry is included to selectively adjust the output of the memory to prevent the possible disorder of lines of the resultant PIP signal on display.
摘要翻译： 具有用于主图像信号和画中画（PIP）信号的调谐器和相关联的解调电路的彩色电视接收机使用单个存储器进行同步并存储PIP信号的单个子采样场。 包括适当的电路以选择性地调节存储器的输出，以防止所显示的所得PIP信号的行的可能的混乱。
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公开(公告)号：US5034907A
公开(公告)日：1991-07-23
申请号：US614043
申请日：1990-11-09
申请人： Brian C. Johnson , Carlo Basile , Amihai Miron , Neil H. E. Weste , Christopher J. Terman , Judson Leonard
发明人： Brian C. Johnson , Carlo Basile , Amihai Miron , Neil H. E. Weste , Christopher J. Terman , Judson Leonard
CPC分类号： G06F15/7867 , G06F7/5443
摘要： A programmable digital signal processor usable in a variety of configurations and controlled by stored coefficients and control words which are addressable to be provided to a plurality of processing sections as often as once per clock cycle. The processor arrangement is suitable for use as a decoder of multiple analog component (MAC) television signals.
摘要翻译： 一种可编程数字信号处理器，可用于各种配置并由可存储的系数和控制字控制，可被寻址以每时钟周期一次提供给多个处理部分。 处理器布置适合用作多个模拟分量（MAC）电视信号的解码器。
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