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21 条记录 (耗时 0.049 秒)

    Architecture for power of two coefficient FIR filter
    1.
    发明授权
    Architecture for power of two coefficient FIR filter 失效
    两系数FIR滤波器的功率结构

    公开(公告)号：US4782458A

    公开(公告)日：1988-11-01

    申请号：US944295

    申请日：1986-12-18

    申请人： Arup K. Bhattacharya ,  Michael G. Cristofalo ,  David Koo ,  Amihai Miron ,  Imran A. Shah

    发明人： Arup K. Bhattacharya ,  Michael G. Cristofalo ,  David Koo ,  Amihai Miron ,  Imran A. Shah

    IPC分类号： G06F17/15 ,  H03H17/02 ,  H03H17/06 ,  G06F15/31

    CPC分类号： H03H17/06 ,  G06F17/15 ,  H03H17/0227 ,  H03H2017/0232

    摘要： An architecture for a very large scale integrated (VLSI) implementation of a finite imprise response (FIR) digital filter having no multipliers and a coefficient space limited to powers of two. The filter structure includes a data bus, a coefficient bus and a sum-in bus to each coefficient tap. Each tap has a coefficient and control word register which is loaded during an initialization phase of the filter. Multiplication is provided by a shifter which provides the correct power of two weighting of an input data sample. The weighted data sample at each tap is added to the output of the previous tap. This architecture results in a regular, modular structure which can be cascaded and which is programmable for various data word lengths and coefficient spaces.

    摘要翻译： 一种用于大规模集成（VLSI）实现的有限扩展响应（FIR）数字滤波器的架构，其没有乘法器和限制为2的幂的系数空间。 滤波器结构包括数据总线，系数总线和到每个系数抽头的总和总线。 每个抽头具有系数和控制字寄存器，它在滤波器的初始化阶段加载。 乘法由提供输入数据样本的两个加权的正确功率的移位器提供。 每个水龙头的加权数据样本将添加到先前水龙头的输出。 该架构产生了可以级联的规则的模块化结构，并且可针对各种数据字长度和系数空间进行编程。

    Fast multiplier architecture
    2.
    发明授权
    Fast multiplier architecture 失效
    快速乘法器架构

    公开(公告)号：US4864529A

    公开(公告)日：1989-09-05

    申请号：US916916

    申请日：1986-10-09

    申请人： Imran A. Shah ,  Arup K. Bhattacharya

    发明人： Imran A. Shah ,  Arup K. Bhattacharya

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5334

    摘要： A digital multiplier circuit which implements a modified multiplier algorithm in binary form and can be implemented as a very large scale integrated circuit. The modified algorithm replaces the large summation required in a typical shift-and-add digital multiplier with the sum of smaller summation terms, both yielding the same product. The digital word representing one of the multiplicands is partitioned or sliced into groups of two or more bits. All possible values of each bit slice are pre-calculated and stored to derive partial products thereof by the other multiplicand. The summation of such partial products rather than of individual bit products reduces the number of partial adders by half or more, depending on the number of bits in each partition or slice.

    摘要翻译： 一种数字乘法器电路，其实现二进制形式的修正乘数算法，并可实现为非常大规模的集成电路。 经修改的算法将典型的移位和加数字乘法器中所需的大量求和与较小的求和项相加，两者产生相同的乘积。 表示被乘数之一的数字字被分割或分成两个或多个位的组。 预先计算和存储每个位片的所有可能的值以通过另一被乘数导出其部分乘积。 这种部分产品而不是单个位产品的总和取决于每个分区或分片中的位数，将部分加法器的数量减少了一半或更多。

    Fast multiplierless architecture for general purpose VLSI FIR digital filters with minimized hardware
    3.
    发明授权
    Fast multiplierless architecture for general purpose VLSI FIR digital filters with minimized hardware 失效
    具有最小化硬件的通用VLSI FIR数字滤波器的快速无乘法架构

    公开(公告)号：US4862402A

    公开(公告)日：1989-08-29

    申请号：US890247

    申请日：1986-07-24

    申请人： Imran A. Shah ,  Arup K. Bhattacharya

    发明人： Imran A. Shah ,  Arup K. Bhattacharya

    IPC分类号： H03H17/02

    CPC分类号： H03H17/0225 ,  H03H17/0233

    摘要： A digital transversal filter which employs a multiplierless algorithm for effecting convolutions of samples of a digital input word by the filter coefficients. Each of the samples of an input word is bit sliced into segments of two or more bits, and convolutions are carried out in parallel on all segments using only adders and registers. The convolution products are then summed in a pipeline adder tree to derive the convolution of the complete input word. This architecture provides high frequency capability and significantly lower transistor count and hardware complexity, enabling efficient very large scale integration (VLSI) implementation.

    摘要翻译： 一种数字横向滤波器，其采用无乘法算法，以通过滤波器系数实现数字输入字的样本的卷积。 输入字的每个样本被比特分割成两个或更多个比特的段，并且使用加法器和寄存器在所有段上并行地执行回旋。 然后将卷积积在流水线加法器树中求和，以导出完整输入字的卷积。 该架构提供高频能力，并显着降低晶体管数量和硬件复杂性，从而实现高效的大规模集成（VLSI）实现。

    Biomarkers of metabolic responses to hepatic drugs
    5.
    发明授权
    Biomarkers of metabolic responses to hepatic drugs 有权
    对肝脏药物的代谢反应的生物标记物

    公开(公告)号：US07807138B2

    公开(公告)日：2010-10-05

    申请号：US11840466

    申请日：2007-08-17

    申请人： Alvin Berger ,  Imran A. Shah

    发明人： Alvin Berger ,  Imran A. Shah

    IPC分类号： A61N49/00

    CPC分类号： G01N33/5014

    摘要： Methods for the measurement and prediction of response to hepatotoxicants and carcinogens through the detection of metabolites in a mammal are provided. The metabolites can be used as biomarkers, including efficacy biomarkers, surrogate biomarkers, and toxicity biomarkers. The methods find use for early prediction of toxicity, target identification/validation, and monitoring of drug efficacy.

    摘要翻译： 提供了通过检测哺乳动物代谢物测量和预测对肝毒素和致癌物质的反应的方法。 代谢物可用作生物标志物，包括功效生物标志物，替代生物标志物和毒性生物标志物。 该方法用于早期预测毒性，靶标鉴定/验证和药物疗效监测。

    Device for splitting a digital interlaced television signal into components
    9.
    发明授权
    Device for splitting a digital interlaced television signal into components 失效
    将数字互联电视信号分解成组件的设备

    公开(公告)号：US5239377A

    公开(公告)日：1993-08-24

    申请号：US898775

    申请日：1992-06-12

    申请人： Imran A. Shah ,  Rob A. Beuker

    发明人： Imran A. Shah ,  Rob A. Beuker

    IPC分类号： H04N7/00 ,  H04N7/01 ,  H04N7/015 ,  H04N7/26 ,  H04N19/00

    CPC分类号： H04N7/015 ,  H04N19/63

    摘要： Device for splitting a digital interlaced television signal into components in which interlaced frames are applied to a vertical low-pass filter (6). To prevent motion artefacts in the spatial signal thus obtained, the interlaced frame is also applied to a vertical high-pass filter (8). This vertical high-pass filter supplies a motion auxiliary signal which may have a small vertical bandwidth. When combining the spatial signal and the motion auxiliary signal, noticeable motion artefacts do not occur in the interlaced frame. The device may be used for deriving a standard television signal from a high-definition television (HDTV) signal and for compatible transmission of HDTV signals.