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公开(公告)号：US20060195218A1
公开(公告)日：2006-08-31
申请号：US11046903
申请日：2005-02-01
Applicant: Asao Yamashita , Merritt Funk , Daniel Prager
Inventor： Asao Yamashita , Merritt Funk , Daniel Prager
IPC: G06F19/00
CPC classification number: H01L22/20 , H01L2924/0002 , H01L2924/00
Abstract: This method includes a method for etch processing that allows the bias between isolated and nested structures/features to be adjusted, correcting for a process wherein the isolated structures/features need to be smaller than the nested structures/features and wherein the nested structures/features need to be reduced relative to the isolated structures/features, while allowing for the critical control of trimming.
Abstract translation: 该方法包括用于蚀刻处理的方法，其允许调整隔离结构/嵌套结构/特征之间的偏置，校正其中隔离结构/特征需要小于嵌套结构/特征的过程，并且其中嵌套结构/特征 需要相对于孤立的结构/特征而减少，同时允许对修剪的关键控制。
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2.发明授权Using Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models for metal-gate structures 有权使用金属栅结构的多层/多输入/多输出（MLMIMO）模型公开(公告)号：US07894927B2
公开(公告)日：2011-02-22
申请号：US12186619
申请日：2008-08-06
Applicant: Merritt Funk , Radha Sundararajan , Asao Yamashita , Daniel Prager , Hyung Joo Lee
Inventor： Merritt Funk , Radha Sundararajan , Asao Yamashita , Daniel Prager , Hyung Joo Lee
CPC classification number: H01L22/12 , H01L22/20 , H01L2924/0002 , H01L2924/00
Abstract: The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes.
Abstract translation: 本发明提供了一种使用多层处理序列和多层/多输入/多输出（MLMIMO）模型以及可以包括一个或多个测量程序，一个或多个聚蚀刻（PE）序列 ，以及一个或多个金属栅极蚀刻序列。 MLMIMO过程控制使用多个层和/或多个过程步骤之间的动态交互行为建模。 多层和/或多个工艺步骤可以与可以使用各向同性和/或各向异性蚀刻工艺产生的线，沟槽，通孔，间隔物，接触和栅极结构的产生相关联。
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3.发明申请Using Multi-Layer/Multi-Input/Multi-Output (MLMIMO) Models for Metal-Gate Structures 有权使用金属门结构的多层/多输入/多输出（MLMIMO）模型公开(公告)号：US20100036518A1
公开(公告)日：2010-02-11
申请号：US12186619
申请日：2008-08-06
Applicant: Merritt Funk , Radha Sundararajan , Asao Yamashita , Daniel Prager , Hyung Joo Lee
Inventor： Merritt Funk , Radha Sundararajan , Asao Yamashita , Daniel Prager , Hyung Joo Lee
IPC: G06F19/00
CPC classification number: H01L22/12 , H01L22/20 , H01L2924/0002 , H01L2924/00
Abstract: The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes.
Abstract translation: 本发明提供了一种使用多层处理序列和多层/多输入/多输出（MLMIMO）模型以及可以包括一个或多个测量程序，一个或多个聚 - 蚀刻（PE）序列 ，以及一个或多个金属栅极蚀刻序列。 MLMIMO过程控制使用多层和/或多个过程步骤之间的动态交互行为建模。 多层和/或多个工艺步骤可以与可以使用各向同性和/或各向异性蚀刻工艺产生的线，沟槽，通孔，间隔物，接触和栅极结构的产生相关联。
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4.发明授权Creating metal gate structures using Lithography-Etch-Lithography-Etch (LELE) processing sequences 有权使用光刻蚀刻 - 刻蚀 - 蚀刻（LELE）处理序列创建金属栅极结构公开(公告)号：US08183062B2
公开(公告)日：2012-05-22
申请号：US12391410
申请日：2009-02-24
Applicant: Merritt Funk , Radha Sundararajan , Asao Yamashita , Daniel Prager
Inventor： Merritt Funk , Radha Sundararajan , Asao Yamashita , Daniel Prager
IPC: H01L21/66
CPC classification number: G03B27/42 , G03F7/70466
Abstract: The invention can provide apparatus and methods of creating metal gate structures on wafers in real-time using Lithography-Etch-Lithography-Etch (LELE) processing sequence. Real-time data and/or historical data associated with LELE processing sequences can be fed forward and/or fed back as fixed variables or constrained variables in internal-Integrated-Metrology modules (i-IMM) to improve the accuracy of the metal gate structures.
Abstract translation: 本发明可以提供使用光刻蚀刻光刻蚀刻（LELE）处理序列实时地在晶片上形成金属栅极结构的设备和方法。 与LELE处理序列相关联的实时数据和/或历史数据可以作为内部集成计量模块（i-IMM）中的固定变量或约束变量进行向前馈送和/或反馈，以提高金属门结构的精度 。
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5.发明授权Creating multi-layer/multi-input/multi-output (MLMIMO) models for metal-gate structures 有权为金属门结构创建多层/多输入/多输出（MLMIMO）模型公开(公告)号：US08019458B2
公开(公告)日：2011-09-13
申请号：US12186668
申请日：2008-08-06
Applicant: Merritt Funk , Radha Sundararajan , Asao Yamashita , Daniel Prager , Hyung Joo Lee
Inventor： Merritt Funk , Radha Sundararajan , Asao Yamashita , Daniel Prager , Hyung Joo Lee
IPC: G06F19/00 , H01L21/00 , H01L21/36 , H01L21/44 , H01L21/31 , G01R31/26 , C30B23/00 , C23F1/00 , H01L39/00
CPC classification number: G05B17/02 , Y10S438/924
Abstract: The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes.
Abstract translation: 本发明提供了一种使用多层处理序列和多层/多输入/多输出（MLMIMO）模型以及可以包括一个或多个测量程序，一个或多个聚蚀刻（PE）序列 ，以及一个或多个金属栅极蚀刻序列。 MLMIMO过程控制使用多层和/或多个过程步骤之间的动态交互行为建模。 多层和/或多个工艺步骤可以与可以使用各向同性和/或各向异性蚀刻工艺产生的线，沟槽，通孔，间隔物，接触和栅极结构的产生相关联。
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Patent Agency Ranking
6.发明授权公开(公告)号：US07899637B2
公开(公告)日：2011-03-01
申请号：US11762563
申请日：2007-06-13
Applicant: Asao Yamashita , Merritt Funk , Daniel Prager , Lee Chen , Radha Sundararajan
Inventor： Asao Yamashita , Merritt Funk , Daniel Prager , Lee Chen , Radha Sundararajan
IPC: B21D22/00
CPC classification number: H01L22/12 , G06F17/5036 , H01L21/67253 , H01L2924/0002 , H01L2924/00
Abstract: The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures.
Abstract translation: 本发明可以提供使用Gate-Optimization处理序列和评估库来处理衬底的方法，所述评估库可包括栅极蚀刻程序，COR蚀刻程序和评估程序。
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7.发明申请公开(公告)号：US20080311688A1
公开(公告)日：2008-12-18
申请号：US11762563
申请日：2007-06-13
Applicant: Asao Yamashita , Merritt Funk , Daniel Prager , Radha Sundararajan , Lee Chen
Inventor： Asao Yamashita , Merritt Funk , Daniel Prager , Radha Sundararajan , Lee Chen
CPC classification number: H01L22/12 , G06F17/5036 , H01L21/67253 , H01L2924/0002 , H01L2924/00
Abstract: The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures.
Abstract translation: 本发明可以提供使用Gate-Optimization处理序列和评估库来处理衬底的方法，所述评估库可以包括栅极蚀刻程序，COR蚀刻程序和评估程序。
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公开(公告)号：US20060064193A1
公开(公告)日：2006-03-23
申请号：US10944463
申请日：2004-09-20
Applicant: Asao Yamashita , Merritt Funk , Daniel Prager
Inventor： Asao Yamashita , Merritt Funk , Daniel Prager
IPC: G06F19/00
CPC classification number: H01L22/20 , H01L21/32139 , H01L2924/0002 , H01L2924/00
Abstract: This method includes a method for etch processing that allows the bias between isolated and nested structures/features to be adjusted, correcting for a process wherein the isolated structures/features need to be smaller than the nested structures/features and wherein the nested structures/features need to be reduced relative to the isolated structures/features, while allowing for the critical control of trimming.
Abstract translation: 该方法包括用于蚀刻处理的方法，其允许调整隔离结构/嵌套结构/特征之间的偏置，校正其中隔离结构/特征需要小于嵌套结构/特征的过程，并且其中嵌套结构/特征 需要相对于孤立的结构/特征而减少，同时允许对修剪的关键控制。
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9.发明申请Creating Multi-Layer/Multi-Input/Multi-Output (MLMIMO) Models for Metal-Gate Structures 有权为金属门结构创建多层/多输入/多输出（MLMIMO）模型公开(公告)号：US20100036514A1
公开(公告)日：2010-02-11
申请号：US12186668
申请日：2008-08-06
Applicant: Merritt Funk , Radha Sundararajan , Asao Yamashita , Daniel Prager , Hyung Joo Lee
Inventor： Merritt Funk , Radha Sundararajan , Asao Yamashita , Daniel Prager , Hyung Joo Lee
IPC: G06F19/00
CPC classification number: G05B17/02 , Y10S438/924
Abstract: The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes.
Abstract translation: 本发明提供了一种使用多层处理序列和多层/多输入/多输出（MLMIMO）模型以及可以包括一个或多个测量程序，一个或多个聚蚀刻（PE）序列 ，以及一个或多个金属栅极蚀刻序列。 MLMIMO过程控制使用多层和/或多个过程步骤之间的动态交互行为建模。 多层和/或多个工艺步骤可以与可以使用各向同性和/或各向异性蚀刻工艺产生的线，沟槽，通孔，间隔物，接触和栅极结构的产生相关联。
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公开(公告)号：US07328418B2
公开(公告)日：2008-02-05
申请号：US11046903
申请日：2005-02-01
Applicant: Asao Yamashita , Merritt Funk , Daniel Prager
Inventor： Asao Yamashita , Merritt Funk , Daniel Prager
CPC classification number: H01L22/20 , H01L2924/0002 , H01L2924/00
Abstract: This method includes a method for etch processing that allows the bias between isolated and nested structures/features to be adjusted, correcting for a process wherein the isolated structures/features need to be smaller than the nested structures/features and wherein the nested structures/features need to be reduced relative to the isolated structures/features, while allowing for the critical control of trimming.
Abstract translation: 该方法包括用于蚀刻处理的方法，其允许调整隔离结构/嵌套结构/特征之间的偏置，校正其中隔离结构/特征需要小于嵌套结构/特征的过程，并且其中嵌套结构/特征 需要相对于孤立的结构/特征而减少，同时允许对修剪的关键控制。
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