公开(公告)号：US20080215935A1

公开(公告)日：2008-09-04

申请号：US12032448

申请日：2008-02-15

Applicant: Ashish Kumar Goel ,  Namerita Khanna ,  Davinder Aggarwal

Inventor： Ashish Kumar Goel ,  Namerita Khanna ,  Davinder Aggarwal

IPC: G06F11/00

CPC classification number: G06F11/1402 ,  G01R31/318519 ,  G06F11/1008

Abstract: In at least some embodiments, a Programmable Logic Device (PLD) is configured to using a counter in conjunction with a threshold value to determine whether a configuration data frame is to be reloaded into a frame register if errors are encountered. In at least other embodiments, a Programmable Logic Device (PLD) is configured to sequentially load configuration data frames into a frame register, check for errors in the configuration data frames during sequentially loading, and correct errors during sequentially loading without reloading one or more previously-loaded different configuration data frames.

Abstract translation: 在至少一些实施例中，可编程逻辑设备（PLD）被配置为结合阈值使用计数器，以确定如果遇到错误，配置数据帧是否被重新加载到帧寄存器中。 在至少其他实施例中，可编程逻辑器件（PLD）被配置为将配置数据帧顺序地加载到帧寄存器中，在顺序加载期间检查配置数据帧中的错误，并且在顺序加载期间校正错误，而不重新加载一个或多个先前 加载不同的配置数据帧。

公开(公告)号：US07271616B2

公开(公告)日：2007-09-18

申请号：US11190509

申请日：2005-07-26

Applicant: Ashish Kumar Goel ,  Davinder Aggarwal

Inventor： Ashish Kumar Goel ,  Davinder Aggarwal

IPC: G06F7/38 ,  H03K19/173

CPC classification number: H03K19/17764 ,  H03K19/17736

Abstract: An improved digital circuit for reducing readback time in field programmable gate arrays (FPGAs) includes a shift register having a plurality of latches and a clock and a reset signal provided to the latches. An interconnect circuit is provided between each pair of latches of the shift register for providing a selective data frame from the desired latch or latches. Connecting a control signal generator to a control input of said interconnect circuit enables quick readback of selected data frames, thereby reducing the time consumed for debugging of an FPGA.

Abstract translation: 用于减小现场可编程门阵列（FPGA）中的回读时间的改进的数字电路包括具有多个锁存器的移位寄存器和提供给锁存器的时钟和复位信号。 在移位寄存器的每对锁存器之间提供互连电路，用于从期望的锁存器或锁存器提供选择性数据帧。 将控制信号发生器连接到所述互连电路的控制输入端可以快速回读所选择的数据帧，从而减少调试FPGA所花费的时间。

公开(公告)号：US07350134B2

公开(公告)日：2008-03-25

申请号：US10667199

申请日：2003-09-18

Applicant: Ashish Kumar Goel ,  Namerita Khanna ,  Davinder Aggarwal

Inventor： Ashish Kumar Goel ,  Namerita Khanna ,  Davinder Aggarwal

IPC: G11C29/00 ,  G06F11/00

CPC classification number: G06F11/1402 ,  G01R31/318519 ,  G06F11/1008

Abstract: An improved method and apparatus for reloading frames in which errors are detected during the Programmable Logic Device configuration. A configuration data frame for a FPGA is loaded to the Frame register of the FPGA and also to an error detection circuit which detects errors with the loaded frame. An error counter value is maintained by the apparatus and is incremented each time an error with a frame is detected. The incremented value is compared by a Comparator circuit with a pre-determined threshold value ‘n’. If a match is found then the configuration process is aborted, else the data frame is reloaded in the configuration memory, transferred again to the frame register and rechecked for errors. If no error is detected with the reloaded frame, the error counter value is reset and the next frame is loaded until the FPGA configuration process is over.

Abstract translation: 一种用于重新加载在可编程逻辑器件配置期间检测到错误的帧的改进的方法和装置。 FPGA的配置数据帧被加载到FPGA的帧寄存器，并且还加载到检测错误的错误检测电路。 错误计数器值由设备维护，并且每当检测到帧的错误时递增。 递增值由具有预定阈值“n”的比较器电路进行比较。 如果发现匹配，则配置过程将中止，否则数据帧将重新加载到配置存储器中，再次传输到帧寄存器并重新检查错误。 如果在重新加载的帧中没有检测到错误，错误计数器值将被复位，下一个帧被加载，直到FPGA配置过程结束。

公开(公告)号：USRE43081E1

公开(公告)日：2012-01-10

申请号：US12136712

申请日：2008-06-10

Applicant: Ashish Kumar Goel ,  Davinder Aggarwal

Inventor： Ashish Kumar Goel ,  Davinder Aggarwal

IPC: H03K19/177

CPC classification number: H03K19/17748 ,  G06F17/5054 ,  H03K19/1776

Abstract: A Programmable Logic Device provides efficient scalability for configuration memory programming while requiring reduced area for implementation. The device includes an array of configuration memory cells, a Vertical Shift Register (VSR) connected to the vertical lines of the array of configuration memory cells, a Select Register (SR) connected to the horizontal lines of the array of configuration memory cells, a Horizontal Shift Register (HSR) providing the enable input to the Select Register (SR), and a Configuration State Machine (CSM) which synchronizes the operations of the VSR, SR and HSR.

Abstract translation: 可编程逻辑器件为配置存储器编程提供了有效的可扩展性，同时需要减少实现的面积。 该装置包括配置存储器单元的阵列，连接到配置存储单元阵列的垂直线的垂直移位寄存器（VSR），连接到配置存储器单元阵列的水平线的选择寄存器（SR）， 提供给选择寄存器（SR）的使能输入的水平移位寄存器（HSR）和与VSR，SR和HSR的操作同步的配置状态机（CSM）。

公开(公告)号：US07774682B2

公开(公告)日：2010-08-10

申请号：US12032448

申请日：2008-02-15

Applicant: Ashish Kumar Goel ,  Namerita Khanna ,  Davinder Aggarwal

Inventor： Ashish Kumar Goel ,  Namerita Khanna ,  Davinder Aggarwal

IPC: G11C29/00 ,  G01R31/28

CPC classification number: G06F11/1402 ,  G01R31/318519 ,  G06F11/1008

Abstract: In at least some embodiments, a Programmable Logic Device (PLD) is configured to using a counter in conjunction with a threshold value to determine whether a configuration data frame is to be reloaded into a frame register if errors are encountered. In at least other embodiments, a Programmable Logic Device (PLD) is configured to sequentially load configuration data frames into a frame register, check for errors in the configuration data frames during sequentially loading, and correct errors during sequentially loading without reloading one or more previously-loaded different configuration data frames.

Abstract translation: 在至少一些实施例中，可编程逻辑设备（PLD）被配置为结合阈值使用计数器，以确定如果遇到错误，配置数据帧是否被重新加载到帧寄存器中。 在至少其他实施例中，可编程逻辑器件（PLD）被配置为将配置数据帧顺序地加载到帧寄存器中，在顺序加载期间检查配置数据帧中的错误，并且在顺序加载期间校正错误，而不重新加载一个或多个先前 加载不同的配置数据帧。

公开(公告)号：US07606969B2

公开(公告)日：2009-10-20

申请号：US11005247

申请日：2004-12-06

Applicant: Davinder Aggarwal ,  Ashish Kumar Goel ,  Namerita Khanna

Inventor： Davinder Aggarwal ,  Ashish Kumar Goel ,  Namerita Khanna

IPC: G06F13/00

CPC classification number: H03K19/17748 ,  H03K19/1776

Abstract: An improved programmable logic device provides increased efficiency and enhanced flexibility in configuration of block memories and includes one or more memory blocks and a vertical shift register that receives the data to be loaded in the memory blocks. The PLD further provides a selection device for selecting the memory cells in the memory blocks that are to store the received data, and a control block for controlling the loading of the data in the memory blocks. The selection device includes an address counter connected to the input of an address decoder so as to enable the selection of addresses in the memory blocks.

Abstract translation: 改进的可编程逻辑器件在块存储器的配置中提供增加的效率和增强的灵活性，并且包括一个或多个存储器块和接收待加载到存储器块中的数据的垂直移位寄存器。 PLD还提供用于选择要存储接收到的数据的存储器块中的存储器单元的选择装置，以及用于控制数据在存储块中的加载的控制块。 选择装置包括与地址解码器的输入连接的地址计数器，以便能够选择存储块中的地址。

公开(公告)号：US07206919B2

公开(公告)日：2007-04-17

申请号：US10319436

申请日：2002-12-13

Applicant: Ashish Kumar Goel ,  Manish Agarwal

Inventor： Ashish Kumar Goel ,  Manish Agarwal

IPC: G06F12/00 ,  G06F13/00

CPC classification number: G06F17/5054

Abstract: A system and method for enabling rapid partial configuration of reconfigurable devices includes a configuration definition unit and a configuration loading unit. The configuration definition unit defines partial configuration requirements, and contains at least a starting address of configuration data for the partial reconfiguration, data size specifying the number of contiguous locations to be reconfigured, and desired configuration data corresponding to the contiguous locations. The configuration loading unit provides for loading the configuration data into the reconfigurable device according to the partial configuration requirements without providing commands corresponding to any addresses outside of said configuration requirements.

Abstract translation: 一种用于实现可重构设备的快速部分配置的系统和方法包括配置定义单元和配置加载单元。 配置定义单元定义部分配置要求，并且至少包含用于部分重配置的配置数据的起始地址，指定要重新配置的连续位置的数量的数据大小以及对应于相邻位置的期望配置数据。 配置加载单元提供根据部分配置要求将配置数据加载到可重新配置设备中，而不提供与所述配置要求之外的任何地址相对应的命令。

公开(公告)号：US07477070B2

公开(公告)日：2009-01-13

申请号：US11294645

申请日：2005-12-05

Applicant: Pramod Kumar Singh ,  Ashish Kumar Goel

Inventor： Pramod Kumar Singh ,  Ashish Kumar Goel

IPC: H03K19/173

CPC classification number: G01R31/31717 ,  G01R31/318519 ,  H03K19/1737 ,  H03K19/17736 ,  H03K19/17764

Abstract: A FPGA device that includes a plurality of programmable logic blocks connected to each other through interconnect resources, one or more sets of registers connected to the interconnect resources for configuring the programmable logic blocks. Additional logic is provided with the registers for selecting an interconnect/logic block testing mode thereby enabling a rapid interconnect/logic testing.

Abstract translation: 一种FPGA器件，其包括通过互连资源彼此连接的多个可编程逻辑块，连接到互连资源的一组或多组寄存器，用于配置可编程逻辑块。 提供附加逻辑用于选择互连/逻辑块测试模式的寄存器，从而实现快速互连/逻辑测试。

公开(公告)号：US06794906B2

公开(公告)日：2004-09-21

申请号：US10269166

申请日：2002-10-10

Applicant: Ashish Kumar Goel ,  Manish Agarwal

Inventor： Ashish Kumar Goel ,  Manish Agarwal

IPC: G11C810

CPC classification number: H03K17/693

Abstract: An improved multi-stage binary hierarchy decoder characterized in that at least one of the decoding stages subsequent to the first stage is implemented as a Transmission Gate Matrix (TGM) in which a single transmission gate enables an active input from the previous stage to its output, thereby resulting in reduced area requirements when implemented as an integrated circuit.