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公开(公告)号：US20080148026A1
公开(公告)日：2008-06-19
申请号：US11611626
申请日：2006-12-15
IPC分类号： G06F9/30
CPC分类号： G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/384 , G06F9/3842 , G06F9/3844 , G06F9/3863
摘要： In one embodiment, a processor comprises a predictor, a checkpoint unit, and circuitry coupled to the checkpoint unit. The predictor is configured to predict an event that can occur during an execution of an instruction operation in the processor. Furthermore, the predictor is configured to provide a confidence indicator corresponding to the prediction. The confidence indicator indicates a relative probability of a correctness of the prediction. The checkpoint unit is configured to store checkpoints of speculative state corresponding to respective instruction operations. Coupled to receive the confidence indicator, the circuitry is configured to save a first checkpoint of speculative state corresponding to the instruction operation if the confidence indicator indicates a first level of probability of correctness. The circuitry is further configured not to save the first checkpoint if the confidence indicator indicates a second level of probability.
摘要翻译： 在一个实施例中，处理器包括预测器，检查点单元和耦合到检查点单元的电路。 预测器被配置为预测在执行处理器中的指令操作期间可能发生的事件。 此外，预测器被配置为提供对应于预测的置信度指标。 置信指标表示预测的正确性的相对概率。 检查点单元被配置为存储对应于各个指令操作的推测状态的检查点。 耦合以接收置信指示器，如果置信指示符指示第一级正确概率，则电路被配置为保存与指令操作相对应的推测状态的第一检查点。 如果置信指示符指示第二级别的概率，则电路还被配置为不保存第一检查点。
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公开(公告)号：US08214602B2
公开(公告)日：2012-07-03
申请号：US12143985
申请日：2008-06-23
IPC分类号： G06F12/00
CPC分类号： G06F9/3842 , G06F9/3834 , G06F12/0831
摘要： In one embodiment, a processor comprises a data cache and a load/store unit (LSU). The LSU comprises a queue and a control unit, and each entry in the queue is assigned to a different load that has accessed the data cache but has not retired. The control unit is configured to update the data cache hit status of each load represented in the queue as a content of the data cache changes. The control unit is configured to detect a snoop hit on a first load in a first entry of the queue responsive to: the snoop index matching a load index stored in the first entry, the data cache hit status of the first load indicating hit, the data cache detecting a snoop hit for the snoop operation, and a load way stored in the first entry matching a first way of the data cache in which the snoop operation is a hit.
摘要翻译： 在一个实施例中，处理器包括数据高速缓存和加载/存储单元（LSU）。 LSU包括队列和控制单元，队列中的每个条目被分配给已访问数据高速缓存但尚未退出的不同负载。 控制单元被配置为随着数据高速缓存的内容改变而更新队列中表示的每个负载的数据高速缓存命中状态。 所述控制单元被配置为响应于：所述窥探索引匹配存储在所述第一条目中的加载索引，所述第一加载指示命中的数据高速缓存命中状态，所述第一加载指示命中的数据高速缓存命中状态， 数据高速缓存检测用于窥探操作的窥探命中，以及存储在第一条目中的加载方式，其与窥探操作是命中的数据高速缓存的第一路径相匹配。
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3.发明授权公开(公告)号：US07861066B2
公开(公告)日：2010-12-28
申请号：US11780684
申请日：2007-07-20
IPC分类号： G06F9/30
CPC分类号： G06F9/3861 , G06F9/3836 , G06F9/3838 , G06F9/3844
摘要： A mechanism for suppressing instruction replay includes a processor having one or more execution units and a scheduler that issue instruction operations for execution by the one or more execution units. The scheduler may also cause instruction operations that are determined to be incorrectly executed to be replayed, or reissued. In addition, a prediction unit within the processor may predict whether a given instruction operation will replay and to provide an indication that the given instruction operation will replay. The processor also includes a decode unit that may decode instructions and in response to detecting the indication, may flag the given instruction operation. The scheduler may further inhibit issue of the flagged instruction operation until a status associated with the flagged instruction is good.
摘要翻译： 用于抑制指令重放的机构包括具有一个或多个执行单元的处理器和发出由一个或多个执行单元执行的指令操作的调度器。 调度器还可以导致被确定为不正确执行以重播或重新发行的指令操作。 此外，处理器内的预测单元可以预测给定指令操作是否将重放，并提供给定指令操作将重放的指示。 处理器还包括解码单元，其可以解码指令并且响应于检测到指示，可以标记给定的指令操作。 调度器可以进一步禁止标记指令操作的发生，直到与被标记的指令相关联的状态良好。
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公开(公告)号：US20090319727A1
公开(公告)日：2009-12-24
申请号：US12143985
申请日：2008-06-23
IPC分类号： G06F12/08
CPC分类号： G06F9/3842 , G06F9/3834 , G06F12/0831
摘要： In one embodiment, a processor comprises a data cache and a load/store unit (LSU). The LSU comprises a queue and a control unit, and each entry in the queue is assigned to a different load that has accessed the data cache but has not retired. The control unit is configured to update the data cache hit status of each load represented in the queue as a content of the data cache changes. The control unit is configured to detect a snoop hit on a first load in a first entry of the queue responsive to: the snoop index matching a load index stored in the first entry, the data cache hit status of the first load indicating hit, the data cache detecting a snoop hit for the snoop operation, and a load way stored in the first entry matching a first way of the data cache in which the snoop operation is a hit.
摘要翻译： 在一个实施例中，处理器包括数据高速缓存和加载/存储单元（LSU）。 LSU包括队列和控制单元，队列中的每个条目被分配给已访问数据高速缓存但尚未退出的不同负载。 控制单元被配置为随着数据高速缓存的内容改变而更新队列中表示的每个负载的数据高速缓存命中状态。 所述控制单元被配置为响应于：所述窥探索引匹配存储在所述第一条目中的加载索引，所述第一加载指示命中的数据高速缓存命中状态，所述第一加载指示命中的数据高速缓存命中状态， 数据高速缓存检测用于窥探操作的窥探命中，以及存储在第一条目中的加载方式，其与窥探操作是命中的数据高速缓存的第一路径相匹配。
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公开(公告)号：US20090024838A1
公开(公告)日：2009-01-22
申请号：US11780684
申请日：2007-07-20
IPC分类号： G06F9/30
CPC分类号： G06F9/3861 , G06F9/3836 , G06F9/3838 , G06F9/3844
摘要： A mechanism for suppressing instruction replay includes a processor having one or more execution units and a scheduler that issue instruction operations for execution by the one or more execution units. The scheduler may also cause instruction operations that are determined to be incorrectly executed to be replayed, or reissued. In addition, a prediction unit within the processor may predict whether a given instruction operation will replay and to provide an indication that the given instruction operation will replay. The processor also includes a decode unit that may decode instructions and in response to detecting the indication, may flag the given instruction operation. The scheduler may further inhibit issue of the flagged instruction operation until a status associated with the flagged instruction is good.
摘要翻译： 用于抑制指令重放的机构包括具有一个或多个执行单元的处理器和发出由一个或多个执行单元执行的指令操作的调度器。 调度器还可以导致被确定为不正确执行以重播或重新发行的指令操作。 此外，处理器内的预测单元可以预测给定指令操作是否将重放，并提供给定指令操作将重放的指示。 处理器还包括解码单元，其可以解码指令并且响应于检测到指示，可以标记给定的指令操作。 调度器可以进一步禁止标记指令操作的发生，直到与被标记的指令相关联的状态良好。
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公开(公告)号：US07502914B2
公开(公告)日：2009-03-10
申请号：US11496225
申请日：2006-07-31
IPC分类号： G06F9/00
CPC分类号： G06F9/3836 , G06F9/3824 , G06F9/3826 , G06F9/3838 , G06F9/384 , G06F9/3861
摘要： In one embodiment, a processor comprises one or more execution resources configured to execute instruction operations and a scheduler coupled to the execution resources. The scheduler is configured to maintain an ancestor tracking vector (ATV) corresponding to each given instruction operation in the scheduler, wherein the ATV identifies instruction operations which can cause the given instruction operation to replay. The scheduler is configured to set the ATV of the given instruction operation to a null value in response to the given instruction operation being dispatched to the scheduler, and is configured to create the ATV of the given instruction operation dynamically as source operands of the given instruction operation are resolved.
摘要翻译： 在一个实施例中，处理器包括被配置为执行指令操作的一个或多个执行资源以及耦合到执行资源的调度器。 调度器被配置为维护与调度器中的每个给定指令操作相对应的祖先跟踪向量（ATV），其中，ATV识别可以使给定指令操作重放的指令操作。 调度器被配置为响应于给定的指令操作被调度到调度器而将给定指令操作的ATV设置为空值，并且被配置为动态地创建给定指令操作的ATV作为给定指令的源操作数 操作得到解决。
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公开(公告)号：US20080028193A1
公开(公告)日：2008-01-31
申请号：US11496225
申请日：2006-07-31
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3824 , G06F9/3826 , G06F9/3838 , G06F9/384 , G06F9/3861
摘要： In one embodiment, a processor comprises one or more execution resources configured to execute instruction operations and a scheduler coupled to the execution resources. The scheduler is configured to maintain an ancestor tracking vector (ATV) corresponding to each given instruction operation in the scheduler, wherein the ATV identifies instruction operations which can cause the given instruction operation to replay. The scheduler is configured to set the ATV of the given instruction operation to a null value in response to the given instruction operation being dispatched to the scheduler, and is configured to create the ATV of the given instruction operation dynamically as source operands of the given instruction operation are resolved.
摘要翻译： 在一个实施例中，处理器包括被配置为执行指令操作的一个或多个执行资源以及耦合到执行资源的调度器。 调度器被配置为维护与调度器中的每个给定指令操作相对应的祖先跟踪向量（ATV），其中，ATV识别可导致给定指令操作重放的指令操作。 调度器被配置为响应于给定的指令操作被调度到调度器而将给定指令操作的ATV设置为空值，并且被配置为动态地创建给定指令操作的ATV作为给定指令的源操作数 操作得到解决。
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