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公开(公告)号：US06999337B2
公开(公告)日：2006-02-14
申请号：US10934301
申请日：2004-09-03
申请人： Astrid Elbe , Wieland Fischer , Norbert Janssen , Tanja Roemer , Holger Sedlak , Jean-Pierre Seifert
发明人： Astrid Elbe , Wieland Fischer , Norbert Janssen , Tanja Roemer , Holger Sedlak , Jean-Pierre Seifert
IPC分类号： G11C11/00
CPC分类号： G11C7/22 , G11C2207/007 , G11C2207/2227
摘要： A register cell includes a first input for a data unit to be written into the register cell. The register cell includes further a second input for a negated data unit to be written into the register cell. A first pair of oppositely coupled inverters as a first storage circuit is adapted to be coupled to the first input. A second pair of oppositely coupled inverters as a second storage circuit is adapted to be coupled to a second input. Using two oppositely coupled pairs of inverters makes it possible to initialize both the first input and the second input of the register either to a high voltage state (precharge) or to a low voltage state (discharge), such that the power consumption of the register cell is homogenized from one working clock to the next.
摘要翻译： 寄存器单元包括要写入寄存器单元的数据单元的第一输入。 寄存器单元还包括要被写入寄存器单元的否定数据单元的第二输入。 作为第一存储电路的第一对相反耦合的反相器适于耦合到第一输入。 作为第二存储电路的第二对相反耦合的反相器适于耦合到第二输入。 使用两个相对耦合的反相器对使得可以将寄存器的第一输入和第二输入初始化为高电压状态（预充电）或低电压状态（放电），使得寄存器的功耗 电池从一个工作时钟均匀化到下一个工作时钟。
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2.发明授权Processor and method for a simultaneous execution of a calculation and a copying process 有权用于同时执行计算和复制过程的处理器和方法公开(公告)号：US07426529B2
公开(公告)日：2008-09-16
申请号：US11006519
申请日：2004-12-06
CPC分类号： G06F9/30014
摘要： A processor includes a source register having a source register content, a destination register, a calculating unit for performing a calculation using the source register content, wherein the calculation is performed in several calculation cycles, and wherein in each cycle only one portion of the source register content is useable, a data bus connected to the source register, the destination register and the calculating unit, and a processor controller. The processor controller is operable to supply the source register content in portions to the calculating unit on the one hand and to the destination register on the other hand during the calculation via the data bus, so that after an execution of the calculation the source register content is written into the destination register. Therefore it is possible to obtain a register copy of a source register the destination register via a limited data bus without additional machine cycles for long operands to be processed in portions.
摘要翻译： 处理器包括具有源寄存器内容的源寄存器，目的地寄存器，用于使用源寄存器内容执行计算的计算单元，其中在几个计算周期中执行计算，并且其中在每个周期中，源的一部分 注册内容可用，连接到源寄存器，目的地寄存器和计算单元的数据总线以及处理器控制器。 处理器控制器可操作以在计算期间通过数据总线将源寄存器内容一部分提供给计算单元，另一方面提供给目标寄存器，使得在执行计算之后，源寄存器内容 被写入目的寄存器。 因此，有可能通过有限的数据总线获得源寄存器的寄存器副本，而不需要额外的机器周期来进行部分处理的长操作数。
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3.发明申请Processor and method for a simultaneous execution of a calculation and a copying process 有权用于同时执行计算和复制过程的处理器和方法公开(公告)号：US20050138337A1
公开(公告)日：2005-06-23
申请号：US11006519
申请日：2004-12-06
CPC分类号： G06F9/30014
摘要： A processor includes a source register having a source register content, a destination register, a calculating unit for performing a calculation using the source register content, wherein the calculation is performed in several calculation cycles, and wherein in each cycle only one portion of the source register content is useable, a data bus connected to the source register, the destination register and the calculating unit, and a processor controller. The processor controller is operable to supply the source register content in portions to the calculating unit on the one hand and to the destination register on the other hand during the calculation via the data bus, so that after an execution of the calculation the source register content is written into the destination register. Therefore it is possible to obtain a register copy of a source register the destination register via a limited data bus without additional machine cycles for long operands to be processed in portions.
摘要翻译： 处理器包括具有源寄存器内容的源寄存器，目的地寄存器，用于使用源寄存器内容执行计算的计算单元，其中在几个计算周期中执行计算，并且其中在每个周期中，源的一部分 注册内容可用，连接到源寄存器，目的地寄存器和计算单元的数据总线以及处理器控制器。 处理器控制器可操作以在计算期间通过数据总线将源寄存器内容一部分提供给计算单元，另一方面提供给目标寄存器，使得在执行计算之后，源寄存器内容 被写入目的寄存器。 因此，有可能通过有限的数据总线获得源寄存器的寄存器副本，而不需要额外的机器周期来进行部分处理的长操作数。
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公开(公告)号：US20050073346A1
公开(公告)日：2005-04-07
申请号：US10934301
申请日：2004-09-03
申请人： Astrid Elbe , Wieland Fischer , Norbert Janssen , Tanja Roemer , Holger Sedlak , Jean-Pierre Seifert
发明人： Astrid Elbe , Wieland Fischer , Norbert Janssen , Tanja Roemer , Holger Sedlak , Jean-Pierre Seifert
CPC分类号： G11C7/22 , G11C2207/007 , G11C2207/2227
摘要： A register cell includes a first input for a data unit to be written into the register cell. The register cell includes further a second input for a negated data unit to be written into the register cell. A first pair of oppositely coupled inverters as a first storage circuit is adapted to be coupled to the first input. A second pair of oppositely coupled inverters as a second storage circuit is adapted to be coupled to a second input. Using two oppositely coupled pairs of inverters makes it possible to initialize both the first input and the second input of the register either to a high voltage state (precharge) or to a low voltage state (discharge), such that the power consumption of the register cell is homogenized from one working clock to the next.
摘要翻译： 寄存器单元包括要写入寄存器单元的数据单元的第一输入。 寄存器单元还包括要被写入寄存器单元的否定数据单元的第二输入。 作为第一存储电路的第一对相反耦合的反相器适于耦合到第一输入。 作为第二存储电路的第二对相反耦合的反相器适于耦合到第二输入。 使用两个相对耦合的反相器对使得可以将寄存器的第一输入和第二输入初始化为高电压状态（预充电）或低电压状态（放电），使得寄存器的功耗 电池从一个工作时钟均匀化到下一个工作时钟。
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公开(公告)号：US20050097156A1
公开(公告)日：2005-05-05
申请号：US10957536
申请日：2004-10-01
CPC分类号： G06F7/506 , G06F7/5052
摘要： Calculating unit having adder blocks, each having single adders, a carry input, a carry output, and a carry pass output, wherein a signal at the carry pass output is indicative of a carry passing through the adder block. Depending on the carry pass output signal, a clock generator for feeding the adder blocks with operands to be processed is decelerated. A determining unit determines in which of the adder blocks a least significant bit of an operand to be subtracted is disposed. A deactivating unit deactivates a carry pass output of adder block(s) provided for lower order digits with respect to the adder block in which the least significant bit is disposed, and a feeding unit feeds a carry into the carry input of this adder block in which the least significant bit is disposed.
摘要翻译： 具有加法器块的计算单元，每个具有单个加法器，进位输入，进位输出和进位通过输出，其中进位通过输出处的信号指示通过加法器块的进位。 根据进位通过输出信号，用于向加法器块馈送要处理的操作数的时钟发生器减速。 确定单元确定在哪个加法器块中设置要减去的操作数的最低有效位。 去激活单元相对于其中布置最低有效位的加法器块去激活为低位数提供的加法器块的进位通过输出，馈送单元将进位馈送到该加法器块的进位输入 其中最低有效位被布置。
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公开(公告)号：US07831650B2
公开(公告)日：2010-11-09
申请号：US11440725
申请日：2006-05-25
IPC分类号： G06F7/38
CPC分类号： G06F7/722
摘要： In a method for modular multiplication using a multiplication look-ahead process for computing a multiplication shift value and a reduction look-ahead process for computing a reduction shift value, a modulus is first transformed into a transformed modulus that is greater than said modulus. The transformation is carried out such that a predetermined fraction of the transformed modulus has a higher-order digit with a first predetermined value that is followed by at least one low-order digit having a second predetermined value. During the iterative working off of the modular multiplication using the multiplication look-ahead process and the reduction look-ahead process, the transformed modulus is utilized so as to obtain at the end of the iteration a transformed result for the modular multiplication. Finally, the transformed result is re-transformed by modular reduction using the original modulus. By means of the transformation according to the invention, iterative working off of the modular multiplication is simplified so that the modular multiplication can be performed faster.
摘要翻译： 在使用用于计算乘法偏移值的乘法预先处理和用于计算减少移位值的减少预先处理的乘法的方法中，首先将模量转换为大于所述模数的变换模数。 进行变换，使得变换模数的预定分数具有具有第一预定值的高阶数字，其后是具有第二预定值的至少一个低位数字。 在使用乘法预先处理和缩小预先处理进行的乘法迭代处理期间，利用变换的模数，以便在迭代结束时获得用于模数乘法的变换结果。 最后，通过使用原始模数的模块化减少来重新转换变换结果。 通过根据本发明的变换，简化了乘法的迭代处理，使得可以更快地执行模乘。
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公开(公告)号：US07120660B2
公开(公告)日：2006-10-10
申请号：US10662627
申请日：2003-09-15
IPC分类号： G06F7/38
CPC分类号： G06F7/722
摘要： In a method for modular multiplication using a multiplication look-ahead process for computing a multiplication shift value and a reduction look-ahead process for computing a reduction shift value, a modulus is first transformed into a transformed modulus that is greater than said modulus. The transformation is carried out such that a predetermined fraction of the transformed modulus has a higher-order digit with a first predetermined value that is followed by at least one low-order digit having a second predetermined value. During the iterative working off of the modular multiplication using the multiplication look-ahead process and the reduction look-ahead process, the transformed modulus is utilized so as to obtain at the end of the iteration a transformed result for the modular multiplication. Finally, the transformed result is re-transformed by modular reduction using the original modulus. By means of the transformation according to the invention, iterative working off of the modular multiplication is simplified so that the modular multiplication can be performed faster.
摘要翻译： 在使用用于计算乘法偏移值的乘法预先处理和用于计算减少移位值的减少预先处理的乘法的方法中，首先将模量转换为大于所述模数的变换模数。 进行变换，使得变换模数的预定分数具有具有第一预定值的高阶数字，其后是具有第二预定值的至少一个低位数字。 在使用乘法预先处理和缩小预先处理进行的乘法迭代处理期间，利用变换的模数，以便在迭代结束时获得用于模数乘法的变换结果。 最后，通过使用原始模数的模块化减少来重新转换变换结果。 通过根据本发明的变换，简化了乘法的迭代处理，使得可以更快地执行模乘。
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公开(公告)号：US06970899B2
公开(公告)日：2005-11-29
申请号：US10957536
申请日：2004-10-01
CPC分类号： G06F7/506 , G06F7/5052
摘要： Calculating unit having adder blocks, each having single adders, a carry input, a carry output, and a carry pass output, wherein a signal at the carry pass output is indicative of a carry passing through the adder block. Depending on the carry pass output signal, a clock generator for feeding the adder blocks with operands to be processed is decelerated. A determining unit determines in which of the adder blocks a least significant bit of an operand to be subtracted is disposed. A deactivating unit deactivates a carry pass output of adder block(s) provided for lower order digits with respect to the adder block in which the least significant bit is disposed, and a feeding unit feeds a carry into the carry input of this adder block in which the least significant bit is disposed.
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公开(公告)号：US20070185948A1
公开(公告)日：2007-08-09
申请号：US11440725
申请日：2006-05-25
IPC分类号： G06F17/14
CPC分类号： G06F7/722
摘要： In a method for modular multiplication using a multiplication look-ahead process for computing a multiplication shift value and a reduction look-ahead process for computing a reduction shift value, a modulus is first transformed into a transformed modulus that is greater than said modulus. The transformation is carried out such that a predetermined fraction of the transformed modulus has a higher-order digit with a first predetermined value that is followed by at least one low-order digit having a second predetermined value. During the iterative working off of the modular multiplication using the multiplication look-ahead process and the reduction look-ahead process, the transformed modulus is utilized so as to obtain at the end of the iteration a transformed result for the modular multiplication. Finally, the transformed result is re-transformed by modular reduction using the original modulus. By means of the transformation according to the invention, iterative working off of the modular multiplication is simplified so that the modular multiplication can be performed faster.
摘要翻译： 在使用用于计算乘法偏移值的乘法预先处理和用于计算减少移位值的减少预先处理的乘法的方法中，首先将模量转换为大于所述模数的变换模数。 进行变换，使得变换模数的预定分数具有具有第一预定值的高阶数字，其后是具有第二预定值的至少一个低位数字。 在使用乘法预先处理和缩小预先处理进行的乘法迭代处理期间，利用变换的模数，以便在迭代结束时获得用于模数乘法的变换结果。 最后，通过使用原始模数的模块化减少来重新转换变换结果。 通过根据本发明的变换，简化了乘法的迭代处理，使得可以更快地执行模乘。
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公开(公告)号：US20050097157A1
公开(公告)日：2005-05-05
申请号：US10959907
申请日：2004-10-06
CPC分类号： G06F7/5052
摘要： A calculating unit comprises several adder blocks with single adders, a clock generator and control means. A carry pass means is associated with each adder block, which determines whether a carry passes fully through the respective adder block. If it is determined that the carry does not pass through any of the adder blocks, the calculating unit is clocked with a clock period, which is sufficient that the carry passes almost fully through an adder block, and passes through at least part of the upstream adder block. If it is determined, that the carry passes fully through an adder block, a panic signal is generated. The adder block is decelerated, so that the clock period is high enough that the carry additionally fully passes through another adder block. Only in a case of panic signals of two adjacent adder blocks, is the calculating unit is decreased so much, that the carry passes from the least significant digit of the calculating unit to the most significant digit of the calculating unit.
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