ADC sequencing
    1.
    发明授权
    ADC sequencing 有权
    ADC测序

    公开(公告)号:US08775694B2

    公开(公告)日:2014-07-08

    申请号:US13624644

    申请日:2012-09-21

    CPC classification number: G06F13/28 H03M1/1215 Y02D10/14

    Abstract: A device comprises a central processing unit (CPU) and a memory configured for storing memory descriptors. The device also includes an analog-to-digital converter controller (ADC controller) configured for managing an analog-to-digital converter (ADC) using the memory descriptors. In addition, the device includes a direct memory access system (DMA system) configured for autonomously sequencing conversion operations performed by the ADC without CPU intervention by transferring the memory descriptors directly between the memory and the ADC controller for controlling the conversion operations performed by the ADC.

    Abstract translation: 一种设备包括中央处理单元(CPU)和配置用于存储存储器描述符的存储器。 该器件还包括配置为使用存储器描述符管理模数转换器(ADC)的模拟 - 数字转换器控制器(ADC控制器)。 另外,该设备还包括直接存储器存取系统(DMA系统),其被配置为通过在存储器和ADC控制器之间直接传送存储器描述符来自动排序由ADC执行的转换操作,而无需CPU干预,以控制由ADC执行的转换操作 。

    ADC sequencing
    2.
    发明授权
    ADC sequencing 有权
    ADC测序

    公开(公告)号:US09032116B2

    公开(公告)日:2015-05-12

    申请号:US14324726

    申请日:2014-07-07

    CPC classification number: G06F13/28 H03M1/1215 Y02D10/14

    Abstract: A device comprises a central processing unit (CPU) and a memory configured for storing memory descriptors. The device also includes an analog-to-digital converter controller (ADC controller) configured for managing an analog-to-digital converter (ADC) using the memory descriptors. In addition, the device includes a direct memory access system (DMA system) configured for autonomously sequencing conversion operations performed by the ADC without CPU intervention by transferring the memory descriptors directly between the memory and the ADC controller for controlling the conversion operations performed by the ADC.

    Abstract translation: 一种设备包括中央处理单元(CPU)和配置用于存储存储器描述符的存储器。 该器件还包括配置为使用存储器描述符管理模数转换器(ADC)的模拟 - 数字转换器控制器(ADC控制器)。 另外,该设备还包括直接存储器存取系统(DMA系统),其被配置为通过在存储器和ADC控制器之间直接传送存储器描述符来自动排序由ADC执行的转换操作,而无需CPU干预,以控制由ADC执行的转换操作 。

    ADC SEQUENCING
    3.
    发明申请

    公开(公告)号:US20140359191A1

    公开(公告)日:2014-12-04

    申请号:US14324726

    申请日:2014-07-07

    CPC classification number: G06F13/28 H03M1/1215 Y02D10/14

    Abstract: A device comprises a central processing unit (CPU) and a memory configured for storing memory descriptors. The device also includes an analog-to-digital converter controller (ADC controller) configured for managing an analog-to-digital converter (ADC) using the memory descriptors. In addition, the device includes a direct memory access system (DMA system) configured for autonomously sequencing conversion operations performed by the ADC without CPU intervention by transferring the memory descriptors directly between the memory and the ADC controller for controlling the conversion operations performed by the ADC.

    ADC SEQUENCING
    4.
    发明申请
    ADC SEQUENCING 有权
    ADC顺序

    公开(公告)号:US20140089536A1

    公开(公告)日:2014-03-27

    申请号:US13624644

    申请日:2012-09-21

    CPC classification number: G06F13/28 H03M1/1215 Y02D10/14

    Abstract: A device comprises a central processing unit (CPU) and a memory configured for storing memory descriptors. The device also includes an analog-to-digital converter controller (ADC controller) configured for managing an analog-to-digital converter (ADC) using the memory descriptors. In addition, the device includes a direct memory access system (DMA system) configured for autonomously sequencing conversion operations performed by the ADC without CPU intervention by transferring the memory descriptors directly between the memory and the ADC controller for controlling the conversion operations performed by the ADC.

    Abstract translation: 一种设备包括中央处理单元(CPU)和配置用于存储存储器描述符的存储器。 该器件还包括配置为使用存储器描述符管理模数转换器(ADC)的模拟 - 数字转换器控制器(ADC控制器)。 另外,该设备还包括直接存储器存取系统(DMA系统),其被配置为通过在存储器和ADC控制器之间直接传送存储器描述符来自动排序由ADC执行的转换操作,而无需CPU干预,以控制由ADC执行的转换操作 。

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