公开(公告)号：US10317978B2

公开(公告)日：2019-06-11

申请号：US15368808

申请日：2016-12-05

Applicant: Atmel Corporation

Inventor： Sebastien Jouin ,  Romain Oddoart ,  Patrice Menard ,  Mickael Le Dily ,  Thierry Gourbilleau

IPC: G06F1/00 ,  G06F1/3234 ,  G06F1/3287 ,  G06F13/16

Abstract: A microcontroller is operable in a low-power mode and includes one or more I/O connectors, as well as an I/O controller operable to provide control signals for controlling a state of a particular one of the I/O connectors. The I/O controller is powered off or deactivated during the low-power mode. The microcontroller also includes I/O connector state control logic operable to control the state of the particular one of the I/O connectors in accordance with the control signals from the I/O controller. The I/O connector state control logic includes I/O connector state retention logic that retains states of the control signals and maintains the particular I/O connector in a corresponding state in accordance with the retained control signals while the microcontroller is in the low-power mode.

公开(公告)号：US09513691B2

公开(公告)日：2016-12-06

申请号：US14716983

申请日：2015-05-20

Applicant: Atmel Corporation

Inventor： Sebastien Jouin ,  Romain Oddoart ,  Patrice Menard ,  Mickael Le Dily ,  Thierry Gourbilleau

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/3287 ,  G06F13/1673 ,  Y02D10/152

Abstract: A microcontroller is operable in a low-power mode and includes one or more I/O connectors, as well as an I/O controller operable to provide control signals for controlling a state of a particular one of the I/O connectors. The I/O controller is powered off or deactivated during the low-power mode. The microcontroller also includes I/O connector state control logic operable to control the state of the particular one of the I/O connectors in accordance with the control signals from the I/O controller. The I/O connector state control logic includes I/O connector state retention logic that retains states of the control signals and maintains the particular I/O connector in a corresponding state in accordance with the retained control signals while the microcontroller is in the low-power mode.

公开(公告)号：US10228752B2

公开(公告)日：2019-03-12

申请号：US15082056

申请日：2016-03-28

Applicant: Atmel Corporation

Inventor： Sebastien Jouin ,  Romain Oddoart ,  Patrice Menard ,  Mickael Le Dily ,  Thierry Gourbilleau

IPC: G06F1/32 ,  G06F1/3296 ,  G06F1/26 ,  G06F9/4401 ,  G06F13/24

Abstract: A voltage scaling system can scale a supply voltage while preventing processor access of system components that are rendered unstable from the scaling. A processor receives an instruction to scale a system supply voltage to a target supply voltage. The processor executes the instruction and enters into a sleep mode. The processor can send, to a controller that saves power, an indication that the processor is in the sleep mode. When the processor is in the sleep mode, the processor becomes inactive and cannot access any components, e.g., Flash memory data, of the voltage scaling system. The controller can configure a voltage regulator to scale the system supply voltage to the target supply voltage. Once the target supply voltage is reached, the voltage regulator sends an interrupt to the processor, thereby waking up the processor from the sleep mode.

公开(公告)号：US09032116B2

公开(公告)日：2015-05-12

申请号：US14324726

申请日：2014-07-07

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Romain Oddoart ,  Cedric Favier

IPC: G06F13/28 ,  H03M1/12 ,  G06F3/05

CPC classification number: G06F13/28 ,  H03M1/1215 ,  Y02D10/14

Abstract: A device comprises a central processing unit (CPU) and a memory configured for storing memory descriptors. The device also includes an analog-to-digital converter controller (ADC controller) configured for managing an analog-to-digital converter (ADC) using the memory descriptors. In addition, the device includes a direct memory access system (DMA system) configured for autonomously sequencing conversion operations performed by the ADC without CPU intervention by transferring the memory descriptors directly between the memory and the ADC controller for controlling the conversion operations performed by the ADC.

Abstract translation: 一种设备包括中央处理单元（CPU）和配置用于存储存储器描述符的存储器。 该器件还包括配置为使用存储器描述符管理模数转换器（ADC）的模拟 - 数字转换器控制器（ADC控制器）。 另外，该设备还包括直接存储器存取系统（DMA系统），其被配置为通过在存储器和ADC控制器之间直接传送存储器描述符来自动排序由ADC执行的转换操作，而无需CPU干预，以控制由ADC执行的转换操作 。

公开(公告)号：US20140359191A1

公开(公告)日：2014-12-04

申请号：US14324726

申请日：2014-07-07

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Romain Oddoart ,  Cedric Favier

IPC: G06F13/28

CPC classification number: G06F13/28 ,  H03M1/1215 ,  Y02D10/14

Abstract: A device comprises a central processing unit (CPU) and a memory configured for storing memory descriptors. The device also includes an analog-to-digital converter controller (ADC controller) configured for managing an analog-to-digital converter (ADC) using the memory descriptors. In addition, the device includes a direct memory access system (DMA system) configured for autonomously sequencing conversion operations performed by the ADC without CPU intervention by transferring the memory descriptors directly between the memory and the ADC controller for controlling the conversion operations performed by the ADC.

公开(公告)号：US20140089536A1

公开(公告)日：2014-03-27

申请号：US13624644

申请日：2012-09-21

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Romain Oddoart ,  Cedric Favier

IPC: G06F13/28

CPC classification number: G06F13/28 ,  H03M1/1215 ,  Y02D10/14

Abstract: A device comprises a central processing unit (CPU) and a memory configured for storing memory descriptors. The device also includes an analog-to-digital converter controller (ADC controller) configured for managing an analog-to-digital converter (ADC) using the memory descriptors. In addition, the device includes a direct memory access system (DMA system) configured for autonomously sequencing conversion operations performed by the ADC without CPU intervention by transferring the memory descriptors directly between the memory and the ADC controller for controlling the conversion operations performed by the ADC.

Abstract translation: 一种设备包括中央处理单元（CPU）和配置用于存储存储器描述符的存储器。 该器件还包括配置为使用存储器描述符管理模数转换器（ADC）的模拟 - 数字转换器控制器（ADC控制器）。 另外，该设备还包括直接存储器存取系统（DMA系统），其被配置为通过在存储器和ADC控制器之间直接传送存储器描述符来自动排序由ADC执行的转换操作，而无需CPU干预，以控制由ADC执行的转换操作 。

公开(公告)号：US20160274654A1

公开(公告)日：2016-09-22

申请号：US15082056

申请日：2016-03-28

Applicant: Atmel Corporation

Inventor： Sebastien Jouin ,  Romain Oddoart ,  Patrice Menard ,  Mickael Le Dily ,  Thierry Gourbilleau

IPC: G06F1/32 ,  G06F13/24 ,  G06F9/44

CPC classification number: G06F1/3296 ,  G06F1/266 ,  G06F9/4418 ,  G06F13/24 ,  Y02D10/172 ,  Y02D50/20

Abstract: A voltage scaling system can scale a supply voltage while preventing processor access of system components that are rendered unstable from the scaling. A processor receives an instruction to scale a system supply voltage to a target supply voltage. The processor executes the instruction and enters into a sleep mode. The processor can send, to a controller that saves power, an indication that the processor is in the sleep mode. When the processor is in the sleep mode, the processor becomes inactive and cannot access any components, e.g., Flash memory data, of the voltage scaling system. The controller can configure a voltage regulator to scale the system supply voltage to the target supply voltage. Once the target supply voltage is reached, the voltage regulator sends an interrupt to the processor, thereby waking up the processor from the sleep mode.

Abstract translation: 电压调节系统可以缩放电源电压，同时防止处理器访问因缩放而变得不稳定的系统组件。 处理器接收将系统电源电压缩放到目标电源电压的指令。 处理器执行指令并进入睡眠模式。 处理器可以向节省电力的控制器发送处理器处于睡眠模式的指示。 当处理器处于睡眠模式时，处理器变为不活动状态，并且不能访问电压缩放系统的任何组件，例如闪存数据。 控制器可以配置电压调节器，以将系统电源电压缩放到目标电源电压。 一旦达到目标电源电压，电压调节器向处理器发送中断，从而将处理器从睡眠模式唤醒。

公开(公告)号：US20170083075A1

公开(公告)日：2017-03-23

申请号：US15368808

申请日：2016-12-05

Applicant: Atmel Corporation

Inventor： Sebastien Jouin ,  Romain Oddoart ,  Patrice Menard ,  Mickael Le Dily ,  Thierry Gourbilleau

IPC: G06F1/32 ,  G06F13/16

CPC classification number: G06F1/3243 ,  G06F1/3287 ,  G06F13/1673 ,  Y02D10/152

Abstract: A microcontroller is operable in a low-power mode and includes one or more I/O connectors, as well as an I/O controller operable to provide control signals for controlling a state of a particular one of the I/O connectors. The I/O controller is powered off or deactivated during the low-power mode. The microcontroller also includes I/O connector state control logic operable to control the state of the particular one of the I/O connectors in accordance with the control signals from the I/O controller. The I/O connector state control logic includes I/O connector state retention logic that retains states of the control signals and maintains the particular I/O connector in a corresponding state in accordance with the retained control signals while the microcontroller is in the low-power mode.

公开(公告)号：US09213397B2

公开(公告)日：2015-12-15

申请号：US13788366

申请日：2013-03-07

Applicant: Atmel Corporation

Inventor： Sebastien Jouin ,  Romain Oddoart ,  Patrice Menard ,  Mickael Le Dily ,  Thierry Gourbilleau

IPC: G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/3296 ,  Y02D10/152 ,  Y02D10/172

Abstract: A microcontroller system can operate in a number of power modes. In response to changing from a previous mode to a present mode, the microcontroller system reads a present calibration value correspond to the present mode from system configuration storage and write the present calibration value to a configuration register for a component. A logic block for the component reads the present calibration value and calibrates the component.

Abstract translation: 微控制器系统可以在多种功率模式下工作。 响应于从先前模式变为当前模式，微控制器系统从系统配置存储读取对应于当前模式的当前校准值，并将当前校准值写入组件的配置寄存器。 组件的逻辑块读取当前校准值并校准组件。

公开(公告)号：US09146887B2

公开(公告)日：2015-09-29

申请号：US13692531

申请日：2012-12-03

Applicant: Atmel Corporation

Inventor： Sebastien Jouin ,  Sylvain Garnier ,  Thierry Delalande ,  Romain Oddoart

IPC: G06F3/00 ,  G09G3/36 ,  G06F13/32

CPC classification number: G06F13/32 ,  G06F13/4234 ,  G09G3/36

Abstract: A device comprises a central processing unit (CPU), a display controller configured for controlling a digital display and a memory configured for storing data corresponding to the digital display. The device includes a direct memory access (DMA) controller configured for autonomously transferring the data from the memory directly to the display controller without CPU intervention.

Abstract translation: 一种设备包括中央处理单元（CPU），被配置为用于控制数字显示器的显示控制器和被配置为存储对应于数字显示器的数据的存储器。 该设备包括直接存储器访问（DMA）控制器，其被配置为在没有CPU干预的情况下将数据从存储器自动地直接传送到显示器控制器。