公开(公告)号：US20080218813A1

公开(公告)日：2008-09-11

申请号：US11763062

申请日：2007-06-14

申请人： Jun TANABE ,  Masaaki ISHIDA ,  Yasuhiro NIHEI ,  Atsufumi OMORI

发明人： Jun TANABE ,  Masaaki ISHIDA ,  Yasuhiro NIHEI ,  Atsufumi OMORI

IPC分类号： H04N1/04

CPC分类号： H04N1/1912 ,  H04N1/0473 ,  H04N1/1917 ,  H04N2201/0082 ,  H04N2201/04787

摘要： A light scanning apparatus is provided that has plural light sources which scan plural light beams in a main scanning direction. The light scanning apparatus comprises a light source control unit that controls the plural light sources. Where an array of N (N≧2) light sources aligned in a sub scanning direction and capable of scanning different positions in the sub scanning direction is called a virtual light source array, and where L (L≧2) virtual light source arrays aligned in the sub scanning direction are formed, the light source control unit causes M ((N−1)≧M≧1) light sources out of the N light sources of each of the L virtual light source arrays to emit light to form a pixel and thereby to form a total of L pixels aligned in the sub scanning direction by giving the same data to the M light sources of each of the L virtual light source arrays.

摘要翻译： 提供一种具有沿主扫描方向扫描多个光束的多个光源的光扫描装置。 光扫描装置包括控制多个光源的光源控制单元。 在副扫描方向上排列并能够在副扫描方向上扫描不同位置的N（N> = 2）个光源的阵列被称为虚拟光源阵列，并且其中L（L> = 2）虚拟光源 形成在副扫描方向上排列的阵列，光源控制单元使得每个L虚拟光源阵列的N个光源中的M（（N-1）> = M> = 1）个光源发光 以形成像素，从而通过向L个虚拟光源阵列中的每一个的M个光源提供相同的数据，形成沿副扫描方向对齐的L个像素的总和。

公开(公告)号：US20080225106A1

公开(公告)日：2008-09-18

申请号：US12029115

申请日：2008-02-11

申请人： Atsufumi OMORI ,  Masaaki ISHIDA ,  Yasuhiro NIHEI ,  Jun TANABE

发明人： Atsufumi OMORI ,  Masaaki ISHIDA ,  Yasuhiro NIHEI ,  Jun TANABE

IPC分类号： B41J2/435

CPC分类号： B41J2/45

摘要： A circuit for driving a plurality of light emitting units includes a current biasing unit that biases a light emitting current with an overshoot current and supplies the resultant current to each of the light emitting units. The light emitting current is determined based on an amount of light emitted from each of the light emitting units.

摘要翻译： 用于驱动多个发光单元的电路包括：电流偏置单元，其利用过冲电流偏置发光电流，并将所得到的电流提供给每个发光单元。 基于从每个发光单元发射的光量来确定发光电流。

公开(公告)号：US20080239336A1

公开(公告)日：2008-10-02

申请号：US12055666

申请日：2008-03-26

申请人： Jun TANABE ,  Masaaki Ishida ,  Yasuhiro Nihei ,  Atsufumi Omori

发明人： Jun TANABE ,  Masaaki Ishida ,  Yasuhiro Nihei ,  Atsufumi Omori

IPC分类号： G06F15/00

CPC分类号： G02B26/123 ,  G02B26/124 ,  H04N1/40068

摘要： A light-source drive control unit divides each pixel of the image data into a plurality of subpixels, deletes certain subpixels from the image data in accordance with predetermined correction data, shifts remaining subpixels in the sub-scanning direction thereby obtaining reduced image data, and controls a plurality of light sources based on the reduced image data in such a manner that one line of the subpixels is formed with a light beam emitted from a corresponding one of the light sources.

摘要翻译： 光源驱动控制单元将图像数据的每个像素分成多个子像素，根据预定的校正数据从图像数据中删除某些子像素，在副扫描方向上移动剩余的子像素，从而获得缩小的图像数据，以及 基于缩小图像数据控制多个光源，使得一行子像素由从相应的一个光源发射的光束形成。

公开(公告)号：US20080256331A1

公开(公告)日：2008-10-16

申请号：US11870173

申请日：2007-10-10

申请人： Jun TANABE

发明人： Jun TANABE

IPC分类号： G06F15/76 ,  G06F9/02

CPC分类号： G06F9/30014 ,  G06F9/30036

摘要： A plurality of general-purpose registers each has a first bit width. A computing unit has a first and a second input end, at least the first input end having a second bit width wider than the first bit width, and performs an arithmetical operation on data supplied from the general-purpose registers to the first and second input ends. An overflow register having a bit width narrower than the first bit width holds data on figures overflowed as a result of calculation by the computing unit as overflow data and supplies the held overflow data as higher-order bits to at least one input end of the computing unit.

摘要翻译： 多个通用寄存器各自具有第一位宽度。 计算单元具​​有第一和第二输入端，至少第一输入端具有比第一位宽宽的第二位宽，并且对从通用寄存器提供给第一和第二输入的数据执行算术运算 结束。 具有比第一位宽窄的位宽的溢出寄存器保存作为计算单元作为溢出数据的计算结果溢出的数据上的数据，并将保持的溢出数据作为高位位提供给计算的至少一个输入端 单元。

公开(公告)号：US20090187749A1

公开(公告)日：2009-07-23

申请号：US12352154

申请日：2009-01-12

申请人： Jun TANABE

发明人： Jun TANABE

IPC分类号： G06F9/30

CPC分类号： G06F9/3867 ,  G06F9/3826

摘要： A bypass circuit is provided in a pipeline processor. A pipeline register is provided between an instruction execution stage and a write-back stage. The pipeline register stores a data validity flag and a WRITE control flag to control writing data into a general purpose register unit. The data retained in the pipeline register is allowed to be written back into the general purpose register unit when the WRITE control flag indicates “valid”. The pipeline register continues to retain the retained data even after the writing of the retained data into the general purpose register unit. The first pipeline register supplies the retained data to the second stage through the bypass circuit at the time of executing a subsequent instruction having data dependency on a preceding instruction.

摘要翻译： 旁路电路设置在流水线处理器中。 在指令执行阶段和回写阶段之间提供流水线寄存器。 流水线寄存器存储数据有效性标志和写入控制标志，以控制将数据写入通用寄存器单元。 当WRITE控制标志指示“有效”时，保留在流水线寄存器中的数据被允许写入通用寄存器单元。 即使在将保留的数据写入通用寄存器单元之后，流水线寄存器继续保留保留的数据。 第一流水线寄存器在执行具有与先前指令有数据依赖关系的后续指令时，通过旁路电路向第二级提供保留数据。

公开(公告)号：US20120062188A1

公开(公告)日：2012-03-15

申请号：US13225798

申请日：2011-09-06

申请人： Jun TANABE

发明人： Jun TANABE

IPC分类号： G05F1/10

CPC分类号： H02M7/48 ,  H02M7/53873 ,  H02M2001/0093

摘要： A power supply device includes an AC generation part having a sinusoidal wave generation part generating a first sinusoidal wave signal, an integrator integrating a difference between the first sinusoidal wave signal and a feedback signal, a triangular wave generation part generating a triangular wave signal, a comparator comparing an output of the integrator and the triangular wave signal and outputting a PWM signal, a switching drive part amplifying the PWM signal and outputs an amplified PWM signal, a filter converting the amplified PWM signal into a second sinusoidal wave signal, a transformer increasing a voltage of the second sinusoidal wave signal and outputting an AC voltage, and a voltage divider dividing the AC voltage and generating the feedback signal, and a DC generation part generating a DC voltage. The power supply device superimposes the AC voltage and the DC voltage and outputs a superimposed voltage.

摘要翻译： 电源装置包括具有生成第一正弦波信号的正弦波生成部的AC生成部，积分第一正弦波信号和反馈信号之间的差的积分器，产生三角波信号的三角波生成部， 比较比较积分器的输出和三角波信号并输出​​PWM信号的开关驱动部分，放大PWM信号并输出​​放大的PWM信号的开关驱动部分，将放大的PWM信号转换成第二正弦波信号的滤波器，变压器增加 第二正弦波信号的电压并输出交流电压，分压器分压交流电压并产生反馈信号，以及直流产生部分产生直流电压。 电源装置叠加交流电压和直流电压，并输出叠加电压。

公开(公告)号：US20110276788A1

公开(公告)日：2011-11-10

申请号：US13187899

申请日：2011-07-21

申请人： Jun TANABE

发明人： Jun TANABE

IPC分类号： G06F9/30

CPC分类号： G06F9/3867 ,  G06F9/3826

摘要： A bypass circuit is provided in a pipeline processor. A pipeline register is provided between an instruction execution stage and a write-back stage. The pipeline register stores a data validity flag and a WRITE control flag to control writing data into a general purpose register unit. The data retained in the pipeline register is allowed to be written back into the general purpose register unit when the WRITE control flag indicates “valid”. The pipeline register continues to retain the retained data even after the writing of the retained data into the general purpose register unit. The first pipeline register supplies the retained data to the second stage through the bypass circuit at the time of executing a subsequent instruction having data dependency on a preceding instruction.

摘要翻译： 旁路电路设置在流水线处理器中。 在指令执行阶段和回写阶段之间提供流水线寄存器。 流水线寄存器存储数据有效性标志和写入控制标志，以控制将数据写入通用寄存器单元。 当WRITE控制标志指示“有效”时，保留在流水线寄存器中的数据被允许写入通用寄存器单元。 即使在将保留的数据写入通用寄存器单元之后，流水线寄存器继续保留保留的数据。 第一流水线寄存器在执行具有与先前指令有数据依赖关系的后续指令时，通过旁路电路向第二级提供保留数据。

公开(公告)号：US20090292857A1

公开(公告)日：2009-11-26

申请号：US12390599

申请日：2009-02-23

申请人： Jun TANABE

发明人： Jun TANABE

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0891

摘要： A cache memory unit temporarily stores data having been stored in a main memory, the valid bits of the flag memory corresponding to the lines of the entries at the to-be-invalidated entry addresses are rewritten so as to indicate invalidation of the lines of the entries at the to-be-invalidated entry addresses, so that the lines of the entries at the to-be-invalidated entry addresses are invalidated.

摘要翻译： 高速缓冲存储器单元临时存储已经存储在主存储器中的数据，重写与被无效的入口地址处的条目的行相对应的标志存储器的有效位，以便指示无效无效的条目地址的行的无效 将要被无效的条目地址的条目，使得被无效的条目地址上的条目的行无效。