公开(公告)号：US20080183931A1

公开(公告)日：2008-07-31

申请号：US11699562

申请日：2007-01-30

Applicant: Atul Verm ,  Samant Kumar

Inventor： Atul Verm ,  Samant Kumar

IPC: G06F12/10 ,  G06F11/07 ,  G06F13/24

CPC classification number: G06F12/10 ,  G06F2212/1032

Abstract: A method or device handles memory management faults in a device having a digital signal processor (“DSP”) and a microprocessor. The DSP includes a memory management unit (“DSP MMU”) to manage memory access by the DSP, and the DSP and the microprocessor access shared physical memory. Upon the DSP executing an instruction attempting to access a virtual address wherein the virtual address is invalid, a page fault interrupt is generated by the DSP MMU. A microprocessor interrupt handler in the microprocessor is activated in direct response to the page fault interrupt. Thereafter in the microprocessor, a translation lookaside buffer (“TLB”) entry is created in the DSP MMU, which includes a valid mapping between the virtual address and a page of physical memory. After creating the TLB entry, the microprocessor indicates to the DSP that the access by the DSP of the virtual address is completed.

Abstract translation: 方法或设备处理具有数字信号处理器（“DSP”）和微处理器的设备中的存储器管理故障。 DSP包括一个内存管理单元（“DSP MMU”），用于管理DSP的存储器访问，DSP和微处理器访问共享的物理内存。 在DSP执行试图访问虚拟地址无效的虚拟地址的指令时，由DSP MMU产生寻呼故障中断。 微处理器中的微处理器中断处理程序是直接响应页错误中断而被激活的。 此后在微处理器中，在DSP MMU中创建翻译后备缓冲器（“TLB”）条目，其包括虚拟地址和物理存储器页之间的有效映射。 在创建TLB条目之后，微处理器向DSP指示DSP访问虚拟地址。