公开(公告)号：US10224952B2

公开(公告)日：2019-03-05

申请号：US15490759

申请日：2017-04-18

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Ali Hadiashar ,  Eric King ,  David Entrikin ,  Wai Lang Lee

IPC: H03M3/00

Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.

公开(公告)号：US10560114B2

公开(公告)日：2020-02-11

申请号：US16174088

申请日：2018-10-29

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Ali Hadiashar ,  Eric King ,  David Entrikin ,  Wai Lang Lee

IPC: H03M3/00

Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.

公开(公告)号：US20190173486A1

公开(公告)日：2019-06-06

申请号：US16174088

申请日：2018-10-29

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Ali Hadiashar ,  Eric King ,  David Entrikin ,  Wai Lang Lee

IPC: H03M3/00

CPC classification number: H03M3/496 ,  H03M3/376 ,  H03M3/438

Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.

公开(公告)号：US20170250703A1

公开(公告)日：2017-08-31

申请号：US15490759

申请日：2017-04-18

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Ali Hadiashar ,  Eric King ,  David Entrikin ,  Wai Lang Lee

IPC: H03M3/00

CPC classification number: H03M3/496 ,  H03M3/376 ,  H03M3/438

Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.

公开(公告)号：US09628106B1

公开(公告)日：2017-04-18

申请号：US15007054

申请日：2016-01-26

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Ali Hadiashar ,  Eric King ,  David Entrikin ,  Wai Lang Lee

IPC: H03M3/00

CPC classification number: H03M3/496 ,  H03M3/376 ,  H03M3/438

Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.