公开(公告)号：US10560114B2

公开(公告)日：2020-02-11

申请号：US16174088

申请日：2018-10-29

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Ali Hadiashar ,  Eric King ,  David Entrikin ,  Wai Lang Lee

IPC: H03M3/00

Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.

公开(公告)号：US20180198430A1

公开(公告)日：2018-07-12

申请号：US15858101

申请日：2017-12-29

Applicant: Avnera Corporation

Inventor： Garry N. Link ,  Eric King ,  Xudong Zhao ,  Wai Lee ,  Alexander C. Stange ,  Amit Kumar

IPC: H03G3/00 ,  H03G3/32

CPC classification number: H03G3/004 ,  H03F1/025 ,  H03F1/305 ,  H03F3/187 ,  H03F2200/507 ,  H03F2200/511 ,  H03G3/32

Abstract: A Class G amplifier system including a processing unit configured to receive an input signal and output a delayed processed input signal, a class G amplifier configured to receive the delayed processed input signal, and a power supply. The power supply includes a regulator configured to operate in a plurality of configurations, each configuration outputs a different supply voltage to the class G amplifier and a control circuit configured to receive the input signal and determine the supply voltage required from the regulator when the delayed processed input signal is received at the class G amplifier, and output a signal to the regulator to indicate the required configuration for the required supply voltage.

公开(公告)号：US20190173486A1

公开(公告)日：2019-06-06

申请号：US16174088

申请日：2018-10-29

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Ali Hadiashar ,  Eric King ,  David Entrikin ,  Wai Lang Lee

IPC: H03M3/00

CPC classification number: H03M3/496 ,  H03M3/376 ,  H03M3/438

Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.

公开(公告)号：US20170250703A1

公开(公告)日：2017-08-31

申请号：US15490759

申请日：2017-04-18

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Ali Hadiashar ,  Eric King ,  David Entrikin ,  Wai Lang Lee

IPC: H03M3/00

CPC classification number: H03M3/496 ,  H03M3/376 ,  H03M3/438

Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.

公开(公告)号：US09628106B1

公开(公告)日：2017-04-18

申请号：US15007054

申请日：2016-01-26

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Ali Hadiashar ,  Eric King ,  David Entrikin ,  Wai Lang Lee

IPC: H03M3/00

CPC classification number: H03M3/496 ,  H03M3/376 ,  H03M3/438

Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.

公开(公告)号：US10425053B2

公开(公告)日：2019-09-24

申请号：US15858101

申请日：2017-12-29

Applicant: Avnera Corporation

Inventor： Garry N. Link ,  Eric King ,  Xudong Zhao ,  Wai Lee ,  Alexander C. Stange ,  Amit Kumar

IPC: H03G3/00 ,  H03G3/32 ,  H03F1/02 ,  H03F1/30 ,  H03F3/187

Abstract: A Class G amplifier system including a processing unit configured to receive an input signal and output a delayed processed input signal, a class G amplifier configured to receive the delayed processed input signal, and a power supply. The power supply includes a regulator configured to operate in a plurality of configurations, each configuration outputs a different supply voltage to the class G amplifier and a control circuit configured to receive the input signal and determine the supply voltage required from the regulator when the delayed processed input signal is received at the class G amplifier, and output a signal to the regulator to indicate the required configuration for the required supply voltage.

公开(公告)号：US20190207575A1

公开(公告)日：2019-07-04

申请号：US16295987

申请日：2019-03-07

Applicant: Avnera Corporation

Inventor： Garry N. Link ,  Eric King ,  Xudong Zhao ,  Wai Lee ,  Alexander C. Stange ,  Amit Kumar

IPC: H03G3/00 ,  H03F1/30 ,  H03F1/02 ,  H03G3/32 ,  H03F3/187

CPC classification number: H03G3/004 ,  H03F1/025 ,  H03F1/305 ,  H03F3/187 ,  H03F2200/507 ,  H03F2200/511 ,  H03G3/32

Abstract: A Class G amplifier system including a processing unit configured to receive an input signal and output a delayed processed input signal, a class G amplifier configured to receive the delayed processed input signal, and a power supply. The power supply includes a regulator configured to operate in a plurality of configurations, each configuration outputs a different supply voltage to the class G amplifier and a control circuit configured to receive the input signal and determine the supply voltage required from the regulator when the delayed processed input signal is received at the class G amplifier, and output a signal to the regulator to indicate the required configuration for the required supply voltage.

公开(公告)号：US10230343B2

公开(公告)日：2019-03-12

申请号：US15858101

申请日：2017-12-29

Applicant: Avnera Corporation

Inventor： Garry N. Link ,  Eric King ,  Xudong Zhao ,  Wai Lee ,  Alexander C. Stange ,  Amit Kumar

IPC: H03G3/00 ,  H03G3/32 ,  H03F1/02 ,  H03F1/30 ,  H03F3/187

Abstract: A Class G amplifier system including a processing unit configured to receive an input signal and output a delayed processed input signal, a class G amplifier configured to receive the delayed processed input signal, and a power supply. The power supply includes a regulator configured to operate in a plurality of configurations, each configuration outputs a different supply voltage to the class G amplifier and a control circuit configured to receive the input signal and determine the supply voltage required from the regulator when the delayed processed input signal is received at the class G amplifier, and output a signal to the regulator to indicate the required configuration for the required supply voltage.

公开(公告)号：US10224952B2

公开(公告)日：2019-03-05

申请号：US15490759

申请日：2017-04-18

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Ali Hadiashar ,  Eric King ,  David Entrikin ,  Wai Lang Lee

IPC: H03M3/00

Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.