公开(公告)号：US10263629B2

公开(公告)日：2019-04-16

申请号：US15991871

申请日：2018-05-29

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Gordon Ueki

IPC: H03M1/36 ,  H03M1/10 ,  H03M1/46

Abstract: The disclosure includes an analog to digital converter (ADC) comprising a successive approximation register (SAR) unit including a capacitive network to take a sample of an analog signal and a comparator to approximate a digital value based on the analog signal sample via successive comparison. The disclosure also includes a programmable sequencer. The sequencer includes a control memory containing control signal states indicating control signals to operate the SAR unit. The sequencer also includes a program memory including sequence instructions defining a duty cycle for the SAR unit by referencing the control signal states in the control memory. The sequencer also includes a processing circuit to apply control signals according to the control signal states in an order defined by the sequence instructions to manage a sequence of operations at the SAR unit according to the duty cycle to control the ADC.

公开(公告)号：US20190245551A1

公开(公告)日：2019-08-08

申请号：US16386188

申请日：2019-04-16

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Gordon Ueki

IPC: H03M1/10

CPC classification number: H03M1/1009 ,  H03M1/1038 ,  H03M1/462 ,  H03M1/466

Abstract: The disclosure includes an analog to digital converter (ADC) comprising a successive approximation register (SAR) unit including a capacitive network to take a sample of an analog signal and a comparator to approximate a digital value based on the analog signal sample via successive comparison. The disclosure also includes a programmable sequencer. The sequencer includes a control memory containing control signal states indicating control signals to operate the SAR unit. The sequencer also includes a program memory including sequence instructions defining a duty cycle for the SAR unit by referencing the control signal states in the control memory. The sequencer also includes a processing circuit to apply control signals according to the control signal states in an order defined by the sequence instructions to manage a sequence of operations at the SAR unit according to the duty cycle to control the ADC.

公开(公告)号：US20180278262A1

公开(公告)日：2018-09-27

申请号：US15991871

申请日：2018-05-29

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Gordon Ueki

IPC: H03M1/10 ,  H03M1/46

CPC classification number: H03M1/1009 ,  H03M1/1038 ,  H03M1/462 ,  H03M1/466

Abstract: The disclosure includes an analog to digital converter (ADC) comprising a successive approximation register (SAR) unit including a capacitive network to take a sample of an analog signal and a comparator to approximate a digital value based on the analog signal sample via successive comparison. The disclosure also includes a programmable sequencer. The sequencer includes a control memory containing control signal states indicating control signals to operate the SAR unit. The sequencer also includes a program memory including sequence instructions defining a duty cycle for the SAR unit by referencing the control signal states in the control memory. The sequencer also includes a processing circuit to apply control signals according to the control signal states in an order defined by the sequence instructions to manage a sequence of operations at the SAR unit according to the duty cycle to control the ADC.

公开(公告)号：US09985640B1

公开(公告)日：2018-05-29

申请号：US15793839

申请日：2017-10-25

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Gordon Ueki

IPC: H03M1/38 ,  H03M1/10 ,  H03M1/46

CPC classification number: H03M1/1009 ,  H03M1/462 ,  H03M1/466

Abstract: The disclosure includes an analog to digital converter (ADC) comprising a successive approximation register (SAR) unit including a capacitive network to take a sample of an analog signal and a comparator to approximate a digital value based on the analog signal sample via successive comparison. The disclosure also includes a programmable sequencer. The sequencer includes a control memory containing control signal states indicating control signals to operate the SAR unit. The sequencer also includes a program memory including sequence instructions defining a duty cycle for the SAR unit by referencing the control signal states in the control memory. The sequencer also includes a processing circuit to apply control signals according to the control signal states in an order defined by the sequence instructions to manage a sequence of operations at the SAR unit according to the duty cycle to control the ADC.