Programmable modular frequency divider

    公开(公告)号:US10742219B1

    公开(公告)日:2020-08-11

    申请号:US16400019

    申请日:2019-04-30

    Abstract: A frequency divider includes a circuit that receives an input clock signal having a period T on an input port thereof and generates an output clock signal on an output port thereof having a period MT in response to a control signal specifying M is disclosed. Here, M is a positive integer and all transitions between logical one and logical zero in the output clock signal occur at integer multiples of T. In one embodiment, the circuit includes a module string having characterized by N identical modules connected in series to form a string of modules. Each module is configured such that when the clock signal having period T is input to the first module, the output clock signal having a period of MT is output from the last module, where M can have any value between one and a maximum number that depends on N.

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