公开(公告)号：US20250071911A1

公开(公告)日：2025-02-27

申请号：US18452984

申请日：2023-08-21

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Nathaniel P. Wyckoff ,  Jacob R. Mauermann ,  Benjamin Terry ,  Justin D. Smith

IPC: H05K3/36

Abstract: A method fabricating at least one universal substrate from a batch product. The method includes steps of: providing a preform having a predetermined profile; wrapping a plurality of conductors about an outer surface of the preform; injecting a nonconductive matrix between conductors of the plurality of conductors, wherein the nonconductive matrix permeates between interstitial spaces of the plurality of conductors to isolate some conductors of the plurality of conductors from one another; forming the batch product that includes the plurality of conductors and the nonconductive matrix; and wafering at least one section of the batch product to form the at least one universal substrate. The plurality of conductors of the at least one universal substrate defines a first connection surface, a second connection surface opposite to the first connection surface, and a plurality of conductive pathways defined between the first connection surface and the second connection surface.

公开(公告)号：US20240413111A1

公开(公告)日：2024-12-12

申请号：US18206731

申请日：2023-06-07

Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

Inventor： Nathaniel P. Wyckoff ,  Alexander S. Warren ,  Jacob R. Mauermann ,  Justin D. Smith

IPC: H01L23/00

Abstract: An integrated circuit structure includes (i) a first layer including a first metal, (ii) a second layer above and in contact with the first layer, the second layer including a resistive material, and (iii) a third layer above and in contact with the second layer, the third layer including a second metal. In an example, the resistive material is different from one or both the first metal and the second metal. An interconnect component is above and in contact with the second layer. In an example, the interconnect component is a solder bump or a solder ball. In an example, a resistivity of the resistive material of the second layer is at least 20%, or at least 50% greater than a resistivity of each of the first and third layers. In an example, the resistive material includes a third metal different from the first and second metals and/or a metalloid.