公开(公告)号：US11971845B2

公开(公告)日：2024-04-30

申请号：US17841720

申请日：2022-06-16

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： David D. Moser ,  Christopher N. Peters ,  Daniel L. Stanley ,  Umair Aslam ,  Elizabeth J. Williams ,  Angelica Sunga

IPC: G06F15/78 ,  G06F13/16 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F15/7817 ,  G06F13/1668 ,  G06F13/385 ,  G06F13/4226 ,  G06F15/7871

Abstract: An encapsulation block for a digital signal processing (DSP) block. The encapsulation block includes DSP block having an input terminal, an output terminal, and an input clock. The encapsulation block also includes pacing control network operatively connected with the input terminal, the output terminal, and the input clock of the DSP block. The input terminal of the DSP block is configured to receive a samples-in data stream inputted at a predefined clock period defined by the input clock. The output terminal of the DSP block is configured to receive a samples-out data stream outputted at a predefined paced parameter. The pacing control network is configured to control data flow at the samples-in data stream and the samples-out data stream independently of the DSP block.

公开(公告)号：US20230409517A1

公开(公告)日：2023-12-21

申请号：US17841720

申请日：2022-06-16

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： David D. Moser ,  Christopher N. Peters ,  Daniel L. Stanley ,  Umair Aslam ,  Elizabeth J. Williams ,  Angelica Sunga

IPC: G06F15/78 ,  G06F13/38 ,  G06F13/16

CPC classification number: G06F15/7817 ,  G06F13/385 ,  G06F15/7871 ,  G06F13/1668

Abstract: An encapsulation block for a digital signal processing (DSP) block. The encapsulation block includes DSP block having an input terminal, an output terminal, and an input clock. The encapsulation block also includes pacing control network operatively connected with the input terminal, the output terminal, and the input clock of the DSP block. The input terminal of the DSP block is configured to receive a samples-in data stream inputted at a predefined clock period defined by the input clock. The output terminal of the DSP block is configured to receive a samples-out data stream outputted at a predefined paced parameter. The pacing control network is configured to control data flow at the samples-in data stream and the samples-out data stream independently of the DSP block.