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公开(公告)号:US3573742A
公开(公告)日:1971-04-06
申请号:US3573742D
申请日:1968-08-06
发明人: RIDDELL GEORGE
CPC分类号: G06F11/14
摘要: A register translator circuit is disclosed which receives plural order binary data from a time division pulse code modulation system and in response thereto, (1) registers the data in storage flip-flops, (2) checks the data for parity, (3) compares the registered data with that subsequently received on a retransmission of the same information, and (4) if the comparison test passes, translates the registered information into a plurality of 1-out-of-N bits. If either the parity or comparison test fails, the input flip-flops are reset and the above operations are repeated until identical data with good parity is received on two successive transmissions. Each data word is represented by a timewise staggered sequence of signals not all of which are overlapping. Because all signals representing a word do not overlap, a comparison circuit is provided which is divided into a first and a second half each of which is individual to a corresponding portion of the data word received on successive transmissions.
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公开(公告)号:US3508255A
公开(公告)日:1970-04-21
申请号:US3508255D
申请日:1967-08-30
发明人: HACKETT JOHN A , RIDDELL GEORGE
CPC分类号: G09G3/10
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公开(公告)号:US3549814A
公开(公告)日:1970-12-22
申请号:US3549814D
申请日:1968-06-17
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公开(公告)号:US3529090A
公开(公告)日:1970-09-15
申请号:US3529090D
申请日:1966-03-24
发明人: RIDDELL GEORGE
CPC分类号: H04Q3/00
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