DATA CACHING CIRCUIT, DISPLAY PANEL AND DISPLAY DEVICE

    公开(公告)号:US20210150959A1

    公开(公告)日:2021-05-20

    申请号:US17007170

    申请日:2020-08-31

    Abstract: A data caching circuit includes a ring signal counter, a switch, and a first latch. An output terminal of the ring signal counter is connected to a control terminal of the switch. An output terminal of the switch is connected to a control terminal of the first latch. The ring signal counter is configured to input a data transmission starting signal and a clock signal to generate and output a count control signal. A clock signal terminal of the switch is configured to input the clock signal, and the switch is configured to generate and output a data caching control signal according to the input count control signal and clock signal. A data signal input terminal of the first latch is configured to input a data signal. The first latch is configured to latch the data signal according to the data caching control signal input from the control terminal of the first latch. An output terminal of the first latch is configured to output the data signal.

    DATA TRANSMISSION CIRCUIT, DISPLAY DEVICE AND DATA TRANSMISSION METHOD

    公开(公告)号:US20210158774A1

    公开(公告)日:2021-05-27

    申请号:US16828464

    申请日:2020-03-24

    Abstract: The embodiments of the present disclosure provide a data transmission circuit, a display device and a data transmission method. The data transmission circuit includes a serial-to-parallel conversion circuit configured to receive serial data and a mode setting signal, generate a mode selection signal according to the mode setting signal, and convert the serial data into parallel data with a corresponding bit width according to the mode selection signal; a control signal generating circuit configured to generate a control signal based on the mode setting signal; and a latch circuit connected to the serial-to-parallel conversion circuit and the control signal generating circuit, and being configured to receive the parallel data from the serial-to-parallel conversion circuit and the control signal from the control signal generating circuit, and latch and output the received parallel data under the control of the control signal.

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