DISPLAY MODULE AND MANUFACTURING METHOD THEREFOR, AND DISPLAY DEVICE

    公开(公告)号:US20230341734A1

    公开(公告)日:2023-10-26

    申请号:US17908426

    申请日:2021-09-02

    CPC classification number: G02F1/136295 G02F1/136209 G02F1/136222

    Abstract: A display module includes a display panel and a dimming panel stacked on the display panel. The display panel has a plurality of pixel The dimming panel a plurality of dimming regions, and in a direction perpendicular to the display panel, a dimming region covers at least one pixel region. The dimming panel includes a plurality of dimming electrodes and a plurality of signal lines. Each dimming electrode is located in dimming region in the plurality of dimming regions, and any two adjacent dimming electrodes have a gap therebetween. Each dimming electrode is directly electrically connected to at least one signal line. The at least one signal line is configured to transmit a control voltage signal to the dimming electrode electrically connected to the at least one signal line for controlling a light transmittance of the dimming region where the dimming electrode is located.

    THIN FILM TRANSISTOR, ARRAY SUBSTRATE AND DISPLAY DEVICE

    公开(公告)号:US20230141490A1

    公开(公告)日:2023-05-11

    申请号:US18093063

    申请日:2023-01-04

    Abstract: A thin film transistor, an array substrate and a display device are provided. The thin film transistor is on a base substrate and includes a gate electrode, a first electrode, and a second electrode on the base substrate. The gate electrode includes a first body portion and a first extension portion extending along the first direction, electrically connected with the first body portion, and spaced apart from the first body portion by a first spacing. The first electrode includes a first overlapping end, an orthographic projection of the first overlapping end on the base substrate at least partially overlaps with an orthographic projection of the first body portion on the base substrate; a first compensation end at a side of the first overlapping end away from the first body portion, an orthographic projection of the first compensation end on the base substrate at least partially overlaps with an orthographic projection of the first extension portion on the base substrate; and a first intermediate portion connecting the first overlapping end and the first compensation end, an orthographic projection of the first intermediate portion on the base substrate is within an orthographic projection of the first spacing on the base substrate.

    DISPLAY PANEL AND DISPLAY DEVICE
    6.
    发明申请

    公开(公告)号:US20220262823A1

    公开(公告)日:2022-08-18

    申请号:US17597882

    申请日:2021-04-20

    Abstract: A display panel includes an opposing substrate and a display substrate. At least one side of the display substrate has a pad area in which gold fingers are arranged. The orthographic projection of the opposing substrate on the display substrate covers the pad area. In a non-display area of the display panel, the opposing substrate and the display substrate are bonded by means of frame sealant. The pad area is located on the outer side of the frame sealant. Side surfaces of the gold fingers are exposed from the side surface of the display substrate. A conductive layer is formed on the side surfaces of the gold fingers. The display panel further includes a flexible buffer layer which is filled between the opposing substrate and the display substrate and covers the gold fingers. The flexible buffer layer is located on the outer side of the frame sealant.

    GATE DRIVING CIRCUIT AND CONTROL METHOD THEREFOR, AND DISPLAY DEVICE

    公开(公告)号:US20220036799A1

    公开(公告)日:2022-02-03

    申请号:US17277352

    申请日:2020-07-14

    Abstract: The present disclosure provides a gate driving circuit, a control method thereof, and a display device. The gate driving circuit includes: an input sub-circuit (110) configured to convert the potential of a first node (N1) from a first level to a second level; an output sub-circuit (120) configured to output a gate driving signal (SOUT); a first reset sub-circuit (130) configured to reset the potential of the first node (N1); at least one noise reduction sub-circuit (140) configured to maintain the potentials of the first node (N1) and an output end of the output sub-circuit (120) at the first level in the case that the potential of the first ode (N1) is reset; and a function maintaining sub-circuit (150) configured to control the noise reduction sub-circuit (140) to operate so that the noise reduction sub-circuit (140) interrupts the first node (N1) and a first voltage terminal.

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