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    VIA-HOLE ETCHING METHOD
    1.
    发明申请
    VIA-HOLE ETCHING METHOD 有权
    通孔蚀刻方法

    公开(公告)号：US20150303099A1

    公开(公告)日：2015-10-22

    申请号：US14361083

    申请日：2013-12-03

    申请人： BOE TECHNOLOGY GROUP CO., LTD. ,  CHENGDU BOE OPTOELETRONICS TECHNOLOGY CO., LTD.

    发明人： Byung Chun LEE ,  Donghua JIANG ,  Yongyi FU ,  Wuyang ZHAO ,  Chundong LI

    IPC分类号： H01L21/768 ,  H01L21/3213 ,  H01L21/311

    CPC分类号： H01L21/76804 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76895

    摘要： The present invention discloses a via-hole etching method related to semiconductor manufacturing field, and the method overcomes the defects of an uncontrollable end point of a via-hole and an unfavorable profile-angle in a conventional via-hole etching method. The via-hole etching method includes: forming a structure for via-hole etching, includes: a low-temperature poly-silicon layer, a gate insulating layer, a gate metal layer and an interlayer insulating layer, which are sequentially formed on a substrate; forming a mask layer comprising a via-hole masking pattern on the structure for via-hole etching; by using a first etching process, etching the structure for via-hole etching to a first thickness of the gate insulating layer; by using a second etching process, etching the structure for via-hole etching to etch away the remaining thickness of the gate insulating layer, and uncovering the low-temperature poly-silicon layer; removing the mask layer to form a via-hole structure.

    摘要翻译： 本发明公开了一种与半导体制造领域相关的通孔蚀刻方法，该方法克服了以往的通孔蚀刻方法中的通孔的不可控端点和不利的形状角的缺陷。 通孔蚀刻方法包括：形成用于通孔蚀刻的结构，包括：顺序地形成在基板上的低温多晶硅层，栅极绝缘层，栅极金属层和层间绝缘层 ; 在所述用于通孔蚀刻的结构上形成包括通孔掩模图案的掩模层; 通过使用第一蚀刻工艺，将用于通孔蚀刻的结构蚀刻到栅极绝缘层的第一厚度; 通过使用第二蚀刻工艺，蚀刻用于通孔蚀刻的结构以蚀刻掉栅极绝缘层的剩余厚度，并露出低温多晶硅层; 去除掩模层以形成通孔结构。