Shift Register and Driving Method Thereof, Gate Driving Circuit and Display Apparatus

    公开(公告)号:US20170358267A1

    公开(公告)日:2017-12-14

    申请号:US15520965

    申请日:2016-01-22

    IPC分类号: G09G3/36 G11C19/28

    摘要: A shift register and driving method thereof, a gate driving circuit and a display apparatus are provided. The shift register includes an input unit, a reset unit, a first control unit, a second control unit, a first output unit, a second output unit, a first signal output end and a second signal output end. Potential of the first signal output end is controlled by use of the input unit, the reset unit, the first control unit and the first output unit, and potential of the second signal output end is controlled by use of the input unit, the reset unit, the second control unit and the second output unit. The first control unit and the first output unit, the second control unit and the second output unit are utilized for controlling and sharing the input unit and the reset unit so that function of two shift register units are realized.

    SHIFT REGISTER UNIT, GATE DRIVING CIRCUIT AND DISPLAY DEVICE

    公开(公告)号:US20170193945A1

    公开(公告)日:2017-07-06

    申请号:US15107846

    申请日:2016-01-13

    发明人: Silin Feng

    IPC分类号: G09G3/36 G11C19/18

    摘要: The present disclosure relates to the field of display technologies, and specifically to a shift register unit, a gate driving circuit comprising the shift register unit and a display device comprising the gate driving circuit. In accordance with an aspect of the present disclosure, a shift register unit is provided, which comprises a set module, a pull-down module, a pull-down control module, a reset module and an output module, wherein the pull-down module is only configured with two transistors to provide discharge channels via the first node and the output terminal, respectively.

    SHIFT REGISTER, DRIVING METHOD THEREOF, GATE DRIVING CIRCUIT AND DISPLAY DEVICE

    公开(公告)号:US20210217350A1

    公开(公告)日:2021-07-15

    申请号:US16649509

    申请日:2019-09-20

    发明人: Qing Yang Silin Feng

    IPC分类号: G09G3/20

    摘要: Embodiments of the present disclosure propose a shift register, a driving method thereof, a gate driving circuit, and a display device. The shift register includes: an inputting sub-circuit, an outputting sub-circuit, a resetting sub-circuit, a pulling-down sub-circuit, a pulling-down controlling sub-circuit, and a voltage regulating sub-circuit. The voltage regulating sub-circuit is coupled to a pulling-down node, a pulling-down controlling node, a second clock signal terminal, a third clock signal terminal, a first voltage signal terminal and a second voltage signal terminal, and is configured to regulate a voltage at the pulling-down controlling node based on a first voltage signal from the first voltage signal terminal and a second voltage signal from the second voltage signal terminal, under a control of the second clock signal from the second clock signal terminal, a third clock signal from the third clock signal terminal, and the voltage at the pulling-down node.

    Shift register circuit, method for driving shift register circuit, gate electrode driving circuit and display device

    公开(公告)号:US10658061B2

    公开(公告)日:2020-05-19

    申请号:US16332193

    申请日:2018-08-21

    IPC分类号: G11C19/28 G09G3/20 G11C19/18

    摘要: A shift register circuit, a driving method, a gate driving circuit, and a display device are provided. The shift register circuit includes a clock signal adjustment circuit and a self-control conduction circuit; the clock signal adjustment circuit includes a first clock signal input terminal, a second clock signal input terminal, and a clock signal adjustment output terminal; the clock signal adjusting circuit is configured to, in the case that the first clock signal and the second clock signal are both at a second level, output a first level via a clock signal adjustment output terminal; the self-control conduction circuit is configured to, in the case that the pull-up node is at the first level, control the clock signal adjustment output terminal connect with a pull-up node, or in the case that the pull-up node is at a second level, disconnect the clock signal adjustment output terminal from the pull-up node.

    Shift register and method of driving the same, gate driving circuit

    公开(公告)号:US11373576B2

    公开(公告)日:2022-06-28

    申请号:US16337135

    申请日:2018-09-21

    IPC分类号: G09G3/20 G11C19/28

    摘要: The present application provides a shift register and a method of driving the same, and a gate driving circuit. In the shift register, an input sub-circuit is configured to output an input signal to a pull-up node under control of a first clock signal of a first clock signal terminal, an output sub-circuit is configured to output a second clock signal of a second clock signal terminal to the output terminal under control of a voltage level of the pull-up node, a reset sub-circuit is configured to reset voltage levels of the pull-up node and the output terminal under control of a voltage level of a pull-down node, and a reset control sub-circuit is configured to control the voltage level of the pull-down node such that the voltage levels of the pull-up node and the output terminal are reset to a level signal.

    Shift register and driving method therefor, gate driving circuit and display device

    公开(公告)号:US11087709B2

    公开(公告)日:2021-08-10

    申请号:US16643059

    申请日:2018-11-12

    发明人: Silin Feng Hongmin Li

    IPC分类号: G09G3/36

    摘要: A shift register includes a first input sub-circuit, a first output sub-circuit, and a second output sub-circuit. The first input sub-circuit is connected to a first input terminal, a pull-up node, and a first control terminal, and the first input sub-circuit is configured to output a voltage of the first control terminal to the pull-up node under control of a voltage of the first input terminal. The first output sub-circuit is connected to the pull-up node, a clock signal terminal, and an output terminal, and the first output sub-circuit is configured to output a first level of the clock signal terminal to the output terminal under control of a voltage of the pull-up node. The second output sub-circuit is connected to the output terminal, a second output control terminal, and a first voltage terminal, and the second output sub-circuit is configured to output a voltage of the first voltage terminal to the output terminal under control of a voltage of the second output control terminal.

    Shift register, gate drive circuit, display panel, and driving method

    公开(公告)号:US11069272B2

    公开(公告)日:2021-07-20

    申请号:US16339554

    申请日:2018-08-29

    IPC分类号: G09G3/20 G11C19/28

    摘要: A shift register, a gate drive circuit, a display panel, and a driving method. The shift register includes: an input circuit, which is connected to a pull-up node and an input signal terminal respectively; an output circuit, which is connected to the pull-up node, a clock signal terminal, a direct current signal terminal and an input terminal respectively, wherein the clock signal terminal provides a clock signal, the direct current signal terminal provides a direct current signal, and the output circuit outputs a scanning signal from the output terminal; and an output pull-down circuit, which is connected to the output circuit. The output circuit is configured to output a scanning signal from the output terminal as one from among the direct current signal and the clock signal when a first output condition is satisfied.

    SHIFT REGISTERS, DRIVING METHODS THEREOF, AND GATE DRIVING CIRCUITS

    公开(公告)号:US20180286302A1

    公开(公告)日:2018-10-04

    申请号:US15793904

    申请日:2017-10-25

    发明人: Silin Feng

    IPC分类号: G09G3/20 G11C19/28

    摘要: The embodiments of the present disclosure disclose a shift register, a method for driving the same, and a gate driving circuit. The shift register may include an inputting circuit, configured to apply a signal at a first signal terminal to a pulling up node; a resetting circuit, configured to apply a signal at a second signal terminal to the pulling up node; an outputting circuit, configured to apply a signal at a first clock terminal to an outputting terminal; a pulling down circuit, configured to apply a signal at a constant level terminal to the pulling up node and the outputting terminal according to the potential at a pulling down node, and to apply a signal at the constant level terminal to the pulling up node and the outputting terminal; a pull-down controlling circuit, configured to control the potential at the pulling down node; and a storage capacitor.