DISPLAY APPARATUS, GATE DRIVER AND METHOD FOR CONTROLLING THE SAME

    公开(公告)号:US20190251928A1

    公开(公告)日:2019-08-15

    申请号:US16056912

    申请日:2018-08-07

    IPC分类号: G09G5/00

    摘要: Embodiments of the disclosure provide a gate driver, a display apparatus and a method for controlling the gate driver. The gate driver comprises a plurality of clock signal terminals; a controlling signal terminal; and N stages of cascaded gate driving circuits. Each of the N stages of cascaded gate driving circuits is configured to pull-up a voltage of an outputting terminal of the gate driving circuit according to a signal at the respective clock signal terminal, and to perform a noise reduction operation according to a signal at the controlling signal terminal. A controller is coupled with the clock signal terminals and the controlling signal terminal, and is configured to detect signals at the plurality of clock signal terminals, and to output a valid level signal to the controlling signal terminal in response to the signal at the clock signal terminal being abnormal.

    DISPLAY SUBSTRATE, METHOD FOR DRIVING THE SAME AND DISPLAY PANEL

    公开(公告)号:US20210201749A1

    公开(公告)日:2021-07-01

    申请号:US16072822

    申请日:2017-11-29

    IPC分类号: G09G3/20 H01L27/12 H01L27/02

    摘要: The present disclosure relates to a display substrate, a method for driving the same, and a display panel. The display substrate includes a base substrate as well as gate lines, data lines and a gate driver on the base substrate, the gate line being connected to the gate driver, and electrostatic rings and control components corresponding to at least one gate line are further disposed on the base substrate, each of the gate lines being connected to the electrostatic ring by a corresponding control component. The electrostatic ring is configured to load a control voltage to turn on the corresponding control component after the display panel is turned off, and the corresponding control component is configured to be turned on to change a voltage on the gate line into a turn-on voltage after the display panel is turned off.

    Shift Register Unit, Gate Driving Circuit, Display Apparatus and Control Method

    公开(公告)号:US20200090613A1

    公开(公告)日:2020-03-19

    申请号:US16335814

    申请日:2018-07-19

    IPC分类号: G09G3/36 G11C19/28

    摘要: There is provided in the present disclosure a shift register unit, including: an input sub-circuit, whose first terminal is coupled to an input signal terminal, and second terminal is coupled to a pull-up node; an output sub-circuit, whose first terminal is coupled to the pull-up node, second terminal is coupled to a clock signal terminal, and third terminal is coupled to an output terminal, and configured to output a clock signal of the clock signal terminal to the output terminal under the control of a level signal of the pull-up node; a first electro-static discharge sub-circuit, whose first terminal is coupled to the pull-up node, second terminal is coupled to an electro-static discharge control terminal, and third terminal is coupled to a ground, and configured to discharge static electricity accumulated at the pull-up node under the control of a level signal of the electro-static discharge control terminal.

    Display apparatus, gate driver and method for controlling the same

    公开(公告)号:US10559278B2

    公开(公告)日:2020-02-11

    申请号:US16056912

    申请日:2018-08-07

    IPC分类号: G06F3/038 G09G5/00

    摘要: Embodiments of the disclosure provide a gate driver, a display apparatus and a method for controlling the gate driver. The gate driver comprises a plurality of clock signal terminals; a controlling signal terminal; and N stages of cascaded gate driving circuits. Each of the N stages of cascaded gate driving circuits is configured to pull-up a voltage of an outputting terminal of the gate driving circuit according to a signal at the respective clock signal terminal, and to perform a noise reduction operation according to a signal at the controlling signal terminal. A controller is coupled with the clock signal terminals and the controlling signal terminal, and is configured to detect signals at the plurality of clock signal terminals, and to output a valid level signal to the controlling signal terminal in response to the signal at the clock signal terminal being abnormal.

    SHIFT REGISTER, GATE DRIVING CIRCUIT, DISPLAY PANEL AND DISPLAY APPARATUS

    公开(公告)号:US20190236995A1

    公开(公告)日:2019-08-01

    申请号:US16156617

    申请日:2018-10-10

    IPC分类号: G09G3/20 G11C19/28

    摘要: Embodiments of the present disclosure provide a shift register, a gate driving circuit, a display panel and a display apparatus. The shift register comprises an inputting sub-circuit, an outputting sub-circuit, a resetting sub-circuit, and a first discharging controlling sub-circuit. The first discharging controlling sub-circuit is coupled to a first controlling signal inputting terminal, a second controlling signal inputting terminal and a signal outputting terminal, and configured to provide a second controlling signal from the second controlling signal inputting terminal to the signal outputting terminal under a control of a first controlling signal from the first controlling signal inputting terminal. The signal outputting terminal is set to a high level by inputting the first controlling signal and the second controlling signal to the shift register.

    Display substrate and display device

    公开(公告)号:US11630359B2

    公开(公告)日:2023-04-18

    申请号:US16473761

    申请日:2018-12-27

    摘要: The present disclosure provides a display substrate and a display device. The display substrate includes a common electrode. The common electrode includes an electrode unit array. The electrode unit array includes a plurality of electrode units. Each of the electrode units corresponds to two adjacent sub-pixels. Each of the electrode units includes a boundary electrode line and an inner region defined by the boundary electrode line. The inner region includes a first region and a second region. The first region includes a plurality of first strip electrode lines having a same longitudinal direction. Two adjacent first strip electrode lines are not connected inside the first region. The second region includes a plurality of second strip electrode lines having a same longitudinal direction. Two adjacent second strip electrode lines are not connected inside the second region.