公开(公告)号：US12073772B2

公开(公告)日：2024-08-27

申请号：US17511335

申请日：2021-10-26

Applicant: BOE Technology Group Co., Ltd.

Inventor： Haoliang Zheng ,  Minghua Xuan ,  Dongni Liu ,  SeungWoo Han ,  Li Xiao ,  Liang Chen ,  Hao Chen ,  Jiao Zhao ,  Qi Qi

IPC: G09G3/32

CPC classification number: G09G3/32 ,  G09G2300/0452 ,  G09G2310/0275 ,  G09G2310/0297

Abstract: Disclosed is an array substrate including multiple first selection circuits with each including at least two first selection transistors and at least two first anticreeping transistors. Each first selection transistor is connected with one first anticreeping transistor in series. When the first selection transistor is turned on by a first turn-on signal from a first control signal terminal, the first anticreeping transistor is turned on by a second turn-on signal from a second control signal terminal. When the first selection transistor is turned off by a first turn-off signal from the first control signal terminal, the first anticreeping transistor is turned off to make the first selection transistors and the data signal terminal disconnected, by a second turn-off signal from the second control signal terminal. A voltage of the first turn-off signal is greater than a voltage of the second turn-off signal.