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公开(公告)号：US20220327988A1
公开(公告)日：2022-10-13
申请号：US17809234
申请日：2022-06-27
发明人： Zuquan HU , Zhenyu ZHANG , Haipeng YANG , Ke DAI
IPC分类号： G09G3/20
摘要： A display device, a gate drive circuit, a shift register and a control method are disclosed. The shift register includes a first shift register unit and a second shift register unit, the first shift register unit is configured to write a first control signal to the first node, and write a first clock signal to the first signal output terminal under control of a voltage of the first node; the second shift register unit is configured to write a second clock signal to the second signal output terminal under control of the voltage of the first node; during time of a frame, the first clock signal and a first input signal provided by a first signal input terminal are pulse signals, and the second clock signal is a DC signal.
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公开(公告)号：US20210358383A1
公开(公告)日：2021-11-18
申请号：US16473076
申请日：2019-01-09
发明人： Zuquan HU , Zhenyu ZHANG , Haipeng YANG , Ke DAI
IPC分类号： G09G3/20
摘要： A display device, a gate drive circuit, a shift register and a control method are disclosed. A first shift register unit of the shift register is configured to write a first control signal to a first node under control of a first input signal, write a first clock signal to a first signal output terminal; a second shift register unit of the shift register is configured to write a second control signal to the first node under control of a second input signal, write a second clock signal to a second signal output terminal; during the first frame, the first clock signal and the first input signal are pulse signals, the second clock signal and the second input signal are DC signals; during the second frame, the first clock signal and the first input signal are DC signals, the second clock signal and the second input signal are pulse signals.
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公开(公告)号：US20210066349A1
公开(公告)日：2021-03-04
申请号：US16925863
申请日：2020-07-10
发明人： Yuntian ZHANG , Zhou RUI , Peng JIANG , Haipeng YANG , Ke DAI , Chunxu ZHANG , Zhonghou WU , Li TIAN
IPC分类号： H01L27/12
摘要： A display panel and a method for manufacturing the same, and a display device is provided. The display panel includes a display area including a plurality of gate lines arranged spaced apart in a first direction and a non-display area including a first and a second non-display area. At least one of the first or the second non-display area includes: a gate driving area including a plurality of gate driving units arranged spaced apart in the first direction and connected to the gate lines, a length of at least one gate driving unit being smaller than a length of a pixel in the first direction; a dummy gate driving area including a plurality of dummy gate driving units arranged spaced apart in the first direction; and a first trace area including a plurality of first traces connected to the dummy gate driving units and an external circuit.
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公开(公告)号：US20240304130A1
公开(公告)日：2024-09-12
申请号：US18026326
申请日：2022-05-16
发明人： Yanting HUANG , Ke DAI , Chunyang NIE , Liugang ZHOU , Yunlu CHEN , Qing LI , Jun WANG , Zhi MENG , Wei SUN , Tianxun XIU , Yue YANG
IPC分类号： G09G3/20
CPC分类号： G09G3/2096 , G09G2300/0413 , G09G2300/0452 , G09G2310/0205 , G09G2310/0213 , G09G2310/0221 , G09G2310/0251 , G09G2320/0613 , G09G2320/10 , G09G2330/021 , G09G2340/0435
摘要： A driving method of a display panel and a display apparatus provided by embodiments of the present disclosure include: when a display mode switching startup instruction is received, a non-counting state is entered. The display panel is driven to display a first set picture, and a current display mode is switched to a target display mode. When a data mode switching completing instruction is received, a counting state is entered.
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公开(公告)号：US20230360579A1
公开(公告)日：2023-11-09
申请号：US17632857
申请日：2020-12-04
发明人： Maoxiu ZHOU , Min CHENG , Yuntian ZHANG , Ke DAI , Haipeng YANG , Xiaoting JIANG , Chunxu ZHANG , Li TIAN , Mengmeng LI
IPC分类号： G09G3/20
CPC分类号： G09G3/2092 , G09G2300/0426 , G09G2310/0286 , G11C19/28
摘要： The present disclosure relates to the field of display technologies and, in particular to a display panel and an electronic device. The display panel comprises: Q rows of first scanning line groups arranged sequentially along a column direction; M columns of second scanning line groups arranged sequentially along a row direction; and at least one gate drive circuit, located on a side of the Q-th row of the first scanning line groups away from the (Q−1)-th row of the first scanning line groups. Each gate drive circuit comprises Q columns of shift register unit groups cascaded in stages. The q-th stage of the shift register unit groups is connected with the q-th row of the first scanning line groups through at least one column of the second scanning line groups. M≥Q>1, 1≤q≤Q, and M, N, Q, q are all positive integers.
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公开(公告)号：US20230092089A1
公开(公告)日：2023-03-23
申请号：US17789141
申请日：2021-05-13
发明人： Chunxu ZHANG , Yuntian ZHANG , Xiaoting JIANG , Haipeng YANG , Ke DAI
IPC分类号： G02F1/1345 , G02F1/1362 , G02F1/1333 , H01L27/12
摘要： Disclosed is an array substrate, a display panel, and a display apparatus, and belongs to the field of displays. The array substrate includes: a base substrate, including a display region and a peripheral region surrounding the display region; a plurality of clock lines, disposed on the base substrate and in the peripheral region, wherein the clock lines extend in a first direction; a plurality of clock leads, disposed on the base substrate and in the peripheral region, wherein the clock leads extend in a second direction, and the first direction intersects with the second direction; a plurality of shift register units, disposed on the base substrate and in the peripheral region, wherein the shift register units are connected to the clock lines by the clock leads; and compensation capacitor plates, disposed on the base substrate and in the peripheral region, wherein the compensation capacitor plates are connected to the clock leads, the compensation capacitor plates and the clock leads are in different layers, and an area of the compensation capacitor plate is negatively correlated with a length of a clock lead connected to the compensation capacitor plate.
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公开(公告)号：US20230038437A1
公开(公告)日：2023-02-09
申请号：US17758337
申请日：2021-08-04
发明人： Lin ZHANG , Yanping LIAO , Lei GUO , Ke DAI , Li TIAN
IPC分类号： G02F1/1335 , G02F1/1347
摘要： The present disclosure provides a display device. The display device includes: a liquid crystal display panel; a liquid crystal light control panel located on the light incident side of the liquid crystal display panel; and at least two haze layers located on the light emitting side of the liquid crystal display panel.
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公开(公告)号：US20220137470A1
公开(公告)日：2022-05-05
申请号：US16975264
申请日：2019-11-28
发明人： Yue DU , Yuntian ZHANG , Liangliang JIANG , Lei GUO , Ke DAI , Jiaqing LIU
IPC分类号： G02F1/1362 , G02F1/1368
摘要： The present disclosure provides an array substrate, a dimming liquid crystal panel and a display panel. The array substrate includes: a first transparent electrode layer with a plurality of slit structures, wherein the first transparent electrode layer includes a plurality of domains with an equal area, the plurality of domains include at least two types of domains, the at least two types of domains are arranged in a mosaic shape; a plurality of gate lines extending along a row direction and a plurality of data lines extending along a column direction, the plurality of gate lines and the plurality of data lines crossing to define a plurality of dimming regions arranged in an array.
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公开(公告)号：US20210223639A1
公开(公告)日：2021-07-22
申请号：US16632161
申请日：2019-05-29
发明人： Chunxu ZHANG , Yuntian ZHANG , Zhonghou WU , Peng JIANG , Yafei DENG , Ke DAI
IPC分类号： G02F1/1362 , G02F1/1368 , H01L27/02 , H01L27/12 , H01L29/786
摘要： An array substrate is disclosed, the array sul cluding: a pixel display transistor having a first source, a first drain, and a first channel region, the first channel region having a first channel length extending between the first source and the first drain; an antistatic transistor having a second source, a second drain, and a second channel region; and a conductive block in the second channel region between the second source and the second drain; wherein the first channel region and second channel region are patterned regions of a same semiconductor material layer; and the conductive block divides the second channel region into a first sub-channel and a second sub-channel.
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公开(公告)号：US20210150962A1
公开(公告)日：2021-05-20
申请号：US17094737
申请日：2020-11-10
发明人： Qing LI , Liugang ZHOU , Ke DAI , Yizhan HAN , Liu HE , Yunyun LIANG , Jun WANG , Zhenlin QU , Jianwei SUN , Yulong XIONG , Tao LI , Yu QUAN , Xiaofeng YIN , Qian ZHOU , Pengjun FANG
IPC分类号： G09G3/20
摘要： A display driving device, a display driving method, a display module and a display device are provided. The display driving device includes: a PWM signal generating circuit configured to generate a PWM signal; a PWM signal acquisition circuit, configured to identify whether the PWM signal output by the PWM signal generating circuit is at a high level or a low level; a gamma voltage debugging circuit, configured to debug a gamma voltage to obtain a first group of gamma voltage reference data corresponding to the PWM signal at the high level and a second group of gamma voltage reference data corresponding to the PWM signal at the low level in each gray-scale image; and a gamma voltage switching circuit.
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