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公开(公告)号：US20240210750A1
公开(公告)日：2024-06-27
申请号：US18598071
申请日：2024-03-07
发明人： Xiaoting JIANG , Ke DAI , Haipeng YANG , Chunxu ZHANG , Min CHENG , Zhou RUI
IPC分类号： G02F1/1335 , G02F1/1333 , G02F1/1343 , G02F1/1347 , G02F1/1362 , G02F1/1368
CPC分类号： G02F1/133512 , G02F1/133388 , G02F1/134309 , G02F1/1347 , G02F1/136227 , G02F1/136286 , G02F1/1368 , G02F2202/16 , G02F2203/48
摘要： A light control panel, having a dimming area and a peripheral area surrounding the dimming area; wherein the light control panel includes a first substrate and a second substrate oppositely disposed, and a first liquid crystal layer therebetween; the first substrate includes a signal connecting line on the first base substrate; the signal connecting line includes a first signal sub-line and a second signal sub-line which are electrically connected together and in different layers; a connecting position between the first signal sub-line and the second signal sub-line is in the peripheral area; and the slot at a position corresponding to the connecting position between the first signal sub-line and the second signal sub-line is formed with a protrusion, and an orthographic projection of the slot on the first base substrate overlaps an orthographic projection of the first signal sub-line on the first base substrate.
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公开(公告)号：US20230360579A1
公开(公告)日：2023-11-09
申请号：US17632857
申请日：2020-12-04
发明人： Maoxiu ZHOU , Min CHENG , Yuntian ZHANG , Ke DAI , Haipeng YANG , Xiaoting JIANG , Chunxu ZHANG , Li TIAN , Mengmeng LI
IPC分类号： G09G3/20
CPC分类号： G09G3/2092 , G09G2300/0426 , G09G2310/0286 , G11C19/28
摘要： The present disclosure relates to the field of display technologies and, in particular to a display panel and an electronic device. The display panel comprises: Q rows of first scanning line groups arranged sequentially along a column direction; M columns of second scanning line groups arranged sequentially along a row direction; and at least one gate drive circuit, located on a side of the Q-th row of the first scanning line groups away from the (Q−1)-th row of the first scanning line groups. Each gate drive circuit comprises Q columns of shift register unit groups cascaded in stages. The q-th stage of the shift register unit groups is connected with the q-th row of the first scanning line groups through at least one column of the second scanning line groups. M≥Q>1, 1≤q≤Q, and M, N, Q, q are all positive integers.
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公开(公告)号：US20230092089A1
公开(公告)日：2023-03-23
申请号：US17789141
申请日：2021-05-13
发明人： Chunxu ZHANG , Yuntian ZHANG , Xiaoting JIANG , Haipeng YANG , Ke DAI
IPC分类号： G02F1/1345 , G02F1/1362 , G02F1/1333 , H01L27/12
摘要： Disclosed is an array substrate, a display panel, and a display apparatus, and belongs to the field of displays. The array substrate includes: a base substrate, including a display region and a peripheral region surrounding the display region; a plurality of clock lines, disposed on the base substrate and in the peripheral region, wherein the clock lines extend in a first direction; a plurality of clock leads, disposed on the base substrate and in the peripheral region, wherein the clock leads extend in a second direction, and the first direction intersects with the second direction; a plurality of shift register units, disposed on the base substrate and in the peripheral region, wherein the shift register units are connected to the clock lines by the clock leads; and compensation capacitor plates, disposed on the base substrate and in the peripheral region, wherein the compensation capacitor plates are connected to the clock leads, the compensation capacitor plates and the clock leads are in different layers, and an area of the compensation capacitor plate is negatively correlated with a length of a clock lead connected to the compensation capacitor plate.
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公开(公告)号：US20240274084A1
公开(公告)日：2024-08-15
申请号：US18022757
申请日：2022-04-21
发明人： Chunxu ZHANG , Ke DAI , Jiantao LIU , Lei GUO , Maoxiu ZHOU , Xiaoting JIANG , Min CHENG , Qi LIU
IPC分类号： G09G3/3266 , G09G3/36
CPC分类号： G09G3/3266 , G09G3/3677 , G09G2300/0426 , G09G2320/0233
摘要： A display panel, including: a substrate including a display region and a non-display region; a second conductive layer including more than one gate line located in the display region, and more than one virtual gate line located in the non-display region; a virtual conductive part, located in the non-display region, where the virtual conductive part is located in a different conductive layer from the virtual gate line, an orthographic projection of the virtual conductive part on the substrate is located within an orthographic projection of the virtual gate line on the substrate, and the virtual conductive part is configured to form an equivalent capacitance with the virtual gate line; and a RC load of the virtual gate line matches with a RC load of the gate line.
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公开(公告)号：US20220308412A1
公开(公告)日：2022-09-29
申请号：US17299678
申请日：2020-09-17
发明人： Chunxu ZHANG , Ke DAI , Haipeng YANG , Yuntian ZHANG , Xiaoting JIANG , Min CHENG
IPC分类号： G02F1/1362 , G02F1/1368
摘要： There is provided a display substrate, including gate lines and data lines, which define pixel units, each pixel unit includes a pixel electrode, at least some pixel units are provided with a conductive bridge line in a same layer as the pixel electrode; in the pixel unit with the conductive bridge line, a first hollow structure is on a first side of a first or second end part of the pixel electrode, an end of the conductive bridge line is in the first hollow structure, a second hollow structure is on a second side of the first end part, an absolute value of a difference between parasitic capacitances respectively formed between the pixel electrode and the data lines on two sides of the pixel electrode and closest thereto is less than or equal to a preset capacitance difference value. A display panel and a display device are further provided.
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公开(公告)号：US20220293539A1
公开(公告)日：2022-09-15
申请号：US17507655
申请日：2021-10-21
发明人： Chunxu ZHANG , Xiaoting JIANG , Min CHENG , Maoxiu ZHOU , Haipeng YANG , Ke DAI
IPC分类号： H01L23/00
摘要： Provided is an array substrate. The array substrate includes at least one pad group disposed in a peripheral region of a base substrate, wherein the at least one pad group includes a sector pad group in which the pads are distributed in a sector shape. Therefore, the bonding yield between the array substrate and the circuit board is increased.
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公开(公告)号：US20220291541A1
公开(公告)日：2022-09-15
申请号：US17530065
申请日：2021-11-18
发明人： Min CHENG , Ke DAI , Haipeng YANG , Maoxiu ZHOU , Xiaoting JIANG , Chunxu ZHANG
IPC分类号： G02F1/1335 , G02F1/1333
摘要： Disclose are a display substrate, a liquid crystal display panel and a display device. The display substrate is provided with a display region. The display substrate includes: a base substrate, and a black matrix arranged on a side of the base substrate. The black matrix includes: a first region corresponding to the display region, and a plurality of frame regions arranged on a periphery of the first region. At least one rectilinear first slit and at least one rectilinear second slit intersecting with the at least one rectilinear first slit are arranged in the at least one of the frame regions, and an extending direction of the at least one rectilinear first slit is same as an extending direction of the at least one of the frame regions.
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