Mura compensation circuit and method, driving circuit and display device

    公开(公告)号:US10403218B2

    公开(公告)日:2019-09-03

    申请号:US15515922

    申请日:2016-05-12

    IPC分类号: G09G3/36 G02F1/133

    摘要: A Mura compensation circuit and method, a driving circuit and a display device are provided. The Mura compensation circuit comprises: a vertical Mura compensation unit, for providing a corresponding gamma voltage to a vertical block Mura region and a vertical non-Mura region of a display panel respectively, to compensate for a vertical Mura phenomenon; and/or a horizontal Mura compensation unit, for providing a corresponding gate drive signal and/or a corresponding charging/discharging control signal to a horizontal block Mura region and a horizontal non-Mura region of a display panel respectively, to compensate for a horizontal Mura phenomenon. The Mura compensation circuit can make the different regions of the display panel have the same display effect, and improve reduction of display quality caused by impedance difference at different positions of the display panel, thereby raising the quality of a picture, and can be promoted and applied widely.

    Array substrate and manufacturing method thereof

    公开(公告)号:US10332807B2

    公开(公告)日:2019-06-25

    申请号:US15567786

    申请日:2017-03-03

    摘要: An array substrate and a manufacturing method thereof are provided. The method for manufacturing the array substrate includes: forming a passivation layer on a base substrate; forming photoresist on the passivation layer, and forming a first photoresist pattern including a photoresist-completely-retained region, a photoresist-partially-retained region and a photoresist-completely-removed region, by exposure and development processes; forming a first through hole in the passivation layer by etching the passivation layer with the first photoresist pattern as a mask; forming a second photoresist pattern by performing ashing on the first photoresist pattern to remove the photoresist in the photoresist-partially-retained region and reduce a thickness of the photoresist in the photoresist-completely-retained region; and etching the passivation layer with the second photoresist pattern as a mask, so as to reduce a thickness of the passivation layer in the photoresist-partially-retained region.