公开(公告)号：US09543752B2

公开(公告)日：2017-01-10

申请号：US14042436

申请日：2013-09-30

Applicant: BROADCOM CORPORATION

Inventor： Jan Roelof Westra ,  Jan Mulder ,  Qiongna Zhang ,  Jeffrey Allan Riley ,  Davide Vecchi

IPC: H02H3/20 ,  H01L23/60 ,  H01L27/02 ,  H01Q1/50

CPC classification number: H02H3/20 ,  H01L23/60 ,  H01L27/0248 ,  H01Q1/50

Abstract: A device for digitally protecting against an overvoltage event may include a front-end circuit, an overvoltage protection circuit, and a protection switch. The protection switch may be coupled to the overvoltage protection circuit and may be configured to decouple the front-end circuit from an external medium, in response to a clamp signal. The overvoltage protection circuit may be configured to detect the overvoltage event at one or more nodes of a circuit. In response to the detection of the overvoltage event, the overvoltage protection circuit may generate the clamp signal to activate the protection switch.

Abstract translation: 用于数字防止过电压事件的装置可以包括前端电路，过电压保护电路和保护开关。 保护开关可以耦合到过电压保护电路，并且可以被配置为响应于钳位信号将前端电路与外部介质去耦。 过电压保护电路可以被配置为检测电路的一个或多个节点处的过电压事件。 响应于过电压事件的检测，过电压保护电路可产生钳位信号以激活保护开关。

公开(公告)号：US09202590B2

公开(公告)日：2015-12-01

申请号：US13962699

申请日：2013-08-08

Applicant: Broadcom Corporation

Inventor： Jeffrey Allan Riley

IPC: H03M9/00 ,  G11C19/00 ,  G11C7/20

CPC classification number: G11C7/1018 ,  G06F1/10 ,  G11C7/20 ,  G11C19/00 ,  H03M9/00

Abstract: A clock control circuit for a parallel in, serial out (PISO) shift register helps save power. The clock control circuit selectively clocks the shift register as it converts a parallel input to a serial output. For example, the clock control circuit may provide clock signals to the flip flops (or other buffers) in the shift register that will receive data elements provided with the parallel input. However, the clock control circuit withholds clock signals from flip flops that will not receive data elements provided with the parallel input, or that have already been received by a particular flip flop. As the parallel loaded input elements propagate serially through the shift register, on each clock cycle an additional memory no longer needs to be clocked. The memory no longer needs to be clocked because that memory has already propagated its loaded input element to the following memory, and no further element provided in the N element parallel loaded data is incoming.

Abstract translation: 并行串行输出（PISO）移位寄存器的时钟控制电路有助于节省功耗。 当时钟控制电路将并行输入转换为串行输出时，时钟控制电路选择性地对移位寄存器进行时钟。 例如，时钟控制电路可以向移位寄存器中的触发器（或其他缓冲器）提供时钟信号，该触发器将接收并行输入提供的数据元素。 然而，时钟控制电路保留来自触发器的时钟信号，该时钟信号将不会接收到提供有并行输入的数据元件，或已经被特定触发器接收的数据元件。 由于并行加载的输入元件通过移位寄存器串行传播，因此在每个时钟周期内，不再需要额外的内存时钟。 内存不再需要时钟，因为内存已经将其加载的输入元素传播到以下内存，并且N元素并行加载的数据中没有提供进一步的元素是进入的。

公开(公告)号：US20150032952A1

公开(公告)日：2015-01-29

申请号：US13962699

申请日：2013-08-08

Applicant: Broadcom Corporation

Inventor： Jeffrey Allan Riley

IPC: G11C7/10

CPC classification number: G11C7/1018 ,  G06F1/10 ,  G11C7/20 ,  G11C19/00 ,  H03M9/00

Abstract: A clock control circuit for a parallel in, serial out (PISO) shift register helps save power. The clock control circuit selectively clocks the shift register as it converts a parallel input to a serial output. For example, the clock control circuit may provide clock signals to the flip flops (or other buffers) in the shift register that will receive data elements provided with the parallel input. However, the clock control circuit withholds clock signals from flip flops that will not receive data elements provided with the parallel input, or that have already been received by a particular flip flop. As the parallel loaded input elements propagate serially through the shift register, on each clock cycle an additional memory no longer needs to be clocked. The memory no longer needs to be clocked because that memory has already propagated its loaded input element to the following memory, and no further element provided in the N element parallel loaded data is incoming.

Abstract translation: 并行串行输出（PISO）移位寄存器的时钟控制电路有助于节省功耗。 当时钟控制电路将并行输入转换为串行输出时，时钟控制电路选择性地对移位寄存器进行时钟。 例如，时钟控制电路可以向移位寄存器中的触发器（或其他缓冲器）提供时钟信号，该触发器将接收并行输入提供的数据元素。 然而，时钟控制电路保留来自触发器的时钟信号，该时钟信号将不会接收到提供有并行输入的数据元件，或已经被特定触发器接收的数据元件。 由于并行加载的输入元件通过移位寄存器串行传播，因此在每个时钟周期内，不再需要额外的内存时钟。 内存不再需要时钟，因为内存已经将其加载的输入元素传播到以下内存，并且N元素并行加载的数据中没有提供进一步的元素是进入的。

公开(公告)号：US20160071557A1

公开(公告)日：2016-03-10

申请号：US14945676

申请日：2015-11-19

Applicant: Broadcom Corporation

Inventor： Jeffrey Allan Riley

IPC: G11C7/10 ,  G06F1/10

CPC classification number: G11C7/1018 ,  G06F1/10 ,  G11C7/20 ,  G11C19/00 ,  H03M9/00

Abstract: A clock control circuit for a parallel in, serial out (PISO) shift register helps save power. The clock control circuit selectively clocks the shift register as it converts a parallel input to a serial output. For example, the clock control circuit may provide clock signals to the flip flops (or other buffers) in the shift register that will receive data elements provided with the parallel input. However, the clock control circuit withholds clock signals from flip flops that will not receive data elements provided with the parallel input, or that have already been received by a particular flip flop. As the parallel loaded input elements propagate serially through the shift register, on each clock cycle an additional memory no longer needs to be clocked. The memory no longer needs to be clocked because that memory has already propagated its loaded input element to the following memory, and no further element provided in the N element parallel loaded data is incoming.