公开(公告)号：US06321303B1

公开(公告)日：2001-11-20

申请号：US09271492

申请日：1999-03-18

申请人： Thomas Alan Hoy ,  Belliappa Manavattira Kuttanna ,  Rajesh Patel ,  Michael Dean Snyder

发明人： Thomas Alan Hoy ,  Belliappa Manavattira Kuttanna ,  Rajesh Patel ,  Michael Dean Snyder

IPC分类号： G06F1208

CPC分类号： G06F12/0831

摘要： A computer and its corresponding cache system includes a cache memory, a buffer unit, and a bus transaction queue. The buffer unit includes a plurality of entries suitable for temporarily storing data, address, and attribute information of operations generated by the CPU. A first operation initiated by the load store unit buffers an operation in a first entry of the buffer unit, which initiates a first transaction to be queued in a first entry of the bus transaction queue where the first transaction in the bus transaction queue points to the first entry in the buffer unit. Preferably, the buffer unit is configured to modify the first transaction from a first transaction type to a second transaction type prior to execution in response to an event that alters the data requirements of the queued transaction. Additional utility is achieved by merging multiple store operation that miss to a common cache line into a single entry. Further benefits is achieved by allowing multiple load misses to the same cache line to be completed from a buffer that reduces cache pipeline stalls.

摘要翻译： 计算机及其对应的缓存系统包括高速缓冲存储器，缓冲器单元和总线事务队列。 缓冲单元包括适于临时存储由CPU生成的操作的数据，地址和属性信息的多个条目。 由加载存储单元启动的第一操作缓冲在缓冲单元的第一条目中的操作，该操作启动要在总线事务队列的第一条目中排队的第一事务，其中总线事务队列中的第一事务指向 缓冲单元中的第一个条目。 优选地，缓冲单元被配置为响应于改变排队交易的数据需求的事件，在执行之前将第一事务从第一事务类型修改为第二事务类型。 通过将多个存储操作错过公用高速缓存行合并到单个条目中来实现附加效用。 通过允许从减少高速缓存管道停顿的缓冲器中完成相同高速缓存行的多个加载错误来实现进一步的益处。

公开(公告)号：US06311254B1

公开(公告)日：2001-10-30

申请号：US09271494

申请日：1999-03-18

申请人： Belliappa Manavattira Kuttanna ,  Rajesh Patel ,  Michael Dean Snyder

发明人： Belliappa Manavattira Kuttanna ,  Rajesh Patel ,  Michael Dean Snyder

IPC分类号： G06F1200

CPC分类号： G06F12/0859

摘要： A cache memory system including a cache memory suitable for coupling to a load/store unit of a CPU, a buffer unit comprised of a plurality of entries each including a data buffer and a corresponding address tag. The system is configured to initiate a data fetch transaction in response to a first store operation that misses in both the cache memory and the buffer unit, to allocate a first entry in the buffer unit, and to write the first store operation's data in the first entry's data buffer. The system is adapted to write data from at least one subsequent store operation into the first entry's data buffer if the subsequent store operation misses in the cache but hits in the first entry of the buffer unit prior to completion of the data fetch transaction. In this manner, the first entry's data buffer includes a composite of the first and subsequent store operations' data. Preferably, the cache system is further configured to merge, upon completion of the data fetch, the fetched data with the store operation data in the first entry's data buffer and to reload the cache memory from the first entry's data buffer. In the preferred embodiment, each buffer unit entry further includes data valid bits that indicate the validity of corresponding portions of the entry's data buffer. In this embodiment, the buffer unit is preferably configured to reload the cache memory from the first buffer unit entry if all of the first entry's data valid bits are set prior to completion of the data fetch transaction thereby affecting a “silent” reload of the cache memory in which no data is ultimately required from memory.

摘要翻译： 一种高速缓冲存储器系统，包括适于耦合到CPU的加载/存储单元的高速缓冲存储器，由包括数据缓冲器和相应的地址标签的多个条目组成的缓冲器单元。 该系统被配置为响应于在高速缓冲存储器和缓冲器单元中丢失的第一存储操作来发起数据提取事务，以在缓冲器单元中分配第一条目，并将第一存储操作的数据写入第一存储操作的第一存储操作 条目的数据缓冲区。 如果随后的存储操作在高速缓存中错过但在数据提取事务完成之前在缓冲单元的第一条目中命中，则系统适于将数据从至少一个后续存储操作写入到第一条目的数据缓冲器中。 以这种方式，第一条目的数据缓冲器包括第一和后续存储操作数据的组合。 优选地，高速缓存系统还被配置为在数据获取完成时，将获取的数据与第一条目的数据缓冲器中的存储操作数据进行合并，并从第一条目的数据缓冲器重新加载高速缓冲存储器。 在优选实施例中，每个缓冲器单元条目还包括指示条目的数据缓冲器的对应部分的有效性的数据有效位。 在该实施例中，缓冲单元优选地被配置为如果在完成数据提取事务之前设置了所有第一条目的数据有效位，从而影响高速缓存的“无声”重新加载，则从第一缓冲单元条目重新加载高速缓冲存储器 内存最终不需要内存的内存。

公开(公告)号：US06269427B1

公开(公告)日：2001-07-31

申请号：US09271493

申请日：1999-03-18

申请人： Belliappa Manavattira Kuttanna ,  Rajesh Patel ,  Michael Dean Snyder

发明人： Belliappa Manavattira Kuttanna ,  Rajesh Patel ,  Michael Dean Snyder

IPC分类号： G06F1208

CPC分类号： G06F9/30043 ,  G06F9/30047 ,  G06F9/3824 ,  G06F12/0831 ,  G06F12/0859

摘要： A cache memory system including a cache memory configured for coupling to a load/store unit of a CPU, a buffer unit coupled to said cache memory, and an operation queue comprising a plurality of entries, wherein each valid operation queue entry points to an entry in the buffer unit. The buffer unit includes a plurality of data buffers and each of the data buffers is associated with a corresponding address tag. The system is configured to initiate a data fetch transaction and allocate an entry in the buffer unit in response to a CPU load operation that misses in both the cache memory and the buffer unit. The cache system is further configured to allocate entries in the operation queue in response to subsequent CPU load operations that miss in the cache memory but hit in the buffer unit prior to completion of the data fetch. Preferably, the system is configured to store the fetched data in the buffer unit entry upon satisfaction of said data fetch and still further configured to satisfy pending load operations in the operation queue from the buffer unit entry. In the preferred embodiment, the system is configured to reload the. cache memory from the buffer unit entry upon satisfying all operation queue entries pointing to the buffer unit entry and, thereafter, to invalidate the buffer unit entry and the operation queue entries. The buffer unit entries preferably each include data valid bits indicative of which portions of data stored in a buffer unit entry are valid.

摘要翻译： 一种高速缓冲存储器系统，包括被配置为耦合到CPU的加载/存储单元的高速缓存存储器，耦合到所述高速缓存存储器的缓冲器单元和包括多个条目的操作队列，其中每个有效操作队列入口指向条目 在缓冲单元中。 缓冲单元包括多个数据缓冲器，并且每个数据缓冲器与相应的地址标签相关联。 该系统被配置为响应于在高速缓冲存储器和缓冲器单元中丢失的CPU加载操作而发起数据提取事务并在缓冲器单元中分配条目。 高速缓存系统还被配置为响应于在高速缓冲存储器中错过的随后的CPU加载操作来在操作队列中分配条目，而在数据提取完成之前在缓冲器单元中命中。 优选地，系统被配置为在满足所述数据提取时将获取的数据存储在缓冲器单元条目中，并且还被配置为满足来自缓冲器单元条目的操作队列中的未决加载操作。 在优选实施例中，系统被配置为重新加载。 满足指向缓冲单元条目的所有操作队列条目，然后使缓冲单元条目和操作队列条目无效，从缓冲单元条目缓存存储器。 缓冲单元条目优选地每个都包括指示存储在缓冲单元条目中的数据的哪些部分有效的数据有效位。

公开(公告)号：US5721867A

公开(公告)日：1998-02-24

申请号：US630870

申请日：1996-04-01

申请人： Belliappa Manavattira Kuttanna ,  Sung-Ho Park ,  Rajesh Bhikhubhai Patel

发明人： Belliappa Manavattira Kuttanna ,  Sung-Ho Park ,  Rajesh Bhikhubhai Patel

IPC分类号： G06F12/08 ,  G06G12/12

CPC分类号： G06F12/0859

摘要： A method and apparatus for executing a single beat write (SBW) store instruction during a cache store linefill operation are disclosed. In accordance with the present disclosure, an address associated with the cache memory store linefill operation is first received. This address comprises a tag portion and an index portion. For the cache store linefill operation, the tag portion of this address is sent to a tag latch while the index portion is sent to a burst index latch. During the cache store linefill operation, a second address associated with the single beat write store instruction is received. This second address also comprises a tag portion and an index portion. In response to a determination that a critical word of the cache memory store linefill has been received, the tag portion of the second address is sent to the tag latch and the index portion of the second address is sent to an SBW index latch. By doing so, the single beat write store instruction may be executed before the completion of the cache store linefill operation.

摘要翻译： 公开了一种用于在高速缓冲存储器线填充操作期间执行单拍写（SBW）存储指令的方法和装置。 根据本公开，首先接收与高速缓冲存储器存储行填充操作相关联的地址。 该地址包括标签部分和索引部分。 对于高速缓存存储器线路填充操作，将该地址的标签部分发送到标签锁存器，同时索引部分被发送到突发索引锁存器。 在高速缓存存储器线路填充操作期间，接收与单节拍写存储指令相关联的第二地址。 该第二地址还包括标签部分和索引部分。 响应于已经接收到高速缓冲存储器存储线路填充的关键字的确定，第二地址的标签部分被发送到标签锁存器，并且第二地址的索引部分被发送到SBW索引锁存器。 通过这样做，可以在高速缓存存储器行填充操作完成之前执行单击写存储指令。

公开(公告)号：US5737751A

公开(公告)日：1998-04-07

申请号：US622254

申请日：1996-03-26

申请人： Rajesh Bhikhubhai Patel ,  Sung-Ho Park ,  Romesh Mangho Jessani ,  Belliappa Manavattira Kuttanna

发明人： Rajesh Bhikhubhai Patel ,  Sung-Ho Park ,  Romesh Mangho Jessani ,  Belliappa Manavattira Kuttanna

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F12/0897

摘要： A data processing system having enhanced memory performance is provided. The data processing system comprises a processor that issues memory requests, a multilevel storage system including a first level cache, a second level cache, and a main memory connected to the processor in a memory hierarchy, and a memory controller. The memory controller retrieves a cache line from main memory, when a memory request for the cache line is received from the processor at the first level cache that causes a miss in both the first level cache and the second level cache. The memory controller loads the retrieved cache line in both the first level cache and the second level cache if the received memory request is a load request, and loads the retrieved cache line in only the first level cache and not the second level cache if the received memory request is a store request. The resultant reduction in reloads to the second level cache enhances memory performance by allowing immediate execution of subsequent memory requests to the second level cache and producing a higher hit rate as a result of the reduction in castouts from the second level cache.

摘要翻译： 提供了具有增强的存储器性能的数据处理系统。 数据处理系统包括发出存储器请求的处理器，包括第一级缓存，第二级高速缓存和连接到存储器层级中的处理器的主存储器的多级存储系统和存储器控制器。 当从第一级高速缓存处理器接收到高速缓存行的存储器请求时，存储器控制器从主存储器中检索高速缓存行，这导致在第一级高速缓存和第二级高速缓存中都存在缺失。 如果接收到的存储器请求是加载请求，则存储器控制器将检索到的高速缓存行加载到第一级高速缓存和第二级高速缓存中，并且将所检索的高速缓存行加载到仅第一级高速缓存中而不是第二级高速缓存 内存请求是一个存储请求。 通过允许将后续存储器请求立即执行到第二级高速缓存并且由于来自第二级高速缓存的丢弃的减少而产生更高的命中率，从而减少重新加载到第二级高速缓存来增强存储器性能。

公开(公告)号：US5974505A

公开(公告)日：1999-10-26

申请号：US927131

申请日：1997-09-02

申请人： Belliappa Manavattira Kuttanna ,  Rajesh Bhikhubhai Patel

发明人： Belliappa Manavattira Kuttanna ,  Rajesh Bhikhubhai Patel

IPC分类号： G06F12/08 ,  G06F13/16

CPC分类号： G06F12/0859 ,  G06F2212/1028 ,  Y02B60/1225

摘要： A method and system for reducing power consumption of a non-blocking cache memory within a data processing system is disclosed. In accordance with a method and system of the present disclosure, a detection unit, having several index-matching bits, is associated with the cache memory within the data processing system. A determination is made as to whether or not there is a match in the cache memory, in response to an occurrence of a cache request while the cache memory is performing a linefill operation. In response to a determination that there is not a match for the cache request in the cache memory, another determination is made as to whether or not there is a match for the cache request with a block of information within the ongoing linefill operation. In response to a determination that there is a match for the cache request with a block of information within the ongoing linefill operation, one of the index-matching bits is set and clocks to the cache memory are turned off temporarily in order to reduce power consumption by the cache memory.

摘要翻译： 公开了一种用于降低数据处理系统内的非阻塞高速缓冲存储器的功耗的方法和系统。 根据本公开的方法和系统，具有多个索引匹配位的检测单元与数据处理系统内的高速缓存存储器相关联。 响应于高速缓冲存储器正在执行行填充操作时缓存请求的发生，确定高速缓冲存储器中是否存在匹配。 响应于高速缓冲存储器中的高速缓存请求不匹配的确定，另外确定在正在进行的行填充操作中是否存在具有信息块的高速缓存请求的匹配。 响应于在正在进行的行填充操作中存在具有信息块的缓存请求的匹配的确定，设置索引匹配位之一并临时关闭高速缓存存储器的时钟以便降低功耗 由缓存存储器。

公开(公告)号：US5873123A

公开(公告)日：1999-02-16

申请号：US670116

申请日：1996-06-25

申请人： Rajesh Bhikhubhai Patel ,  Gunendran Thuraisingham ,  Belliappa Manavattira Kuttanna

发明人： Rajesh Bhikhubhai Patel ,  Gunendran Thuraisingham ,  Belliappa Manavattira Kuttanna

IPC分类号： G06F12/10

CPC分类号： G06F12/1018

摘要： A processor and method for translating a nonphysical address into a physical address are disclosed. A determination is made if a first entry set which could contain a particular entry that associates a selected nonphysical address with a corresponding physical address assigned to a device in the data processing system is stored within a first memory of the data processing system. In response to a determination that the first entry set is not stored in the first memory, a determination is made if a second entry set which could contain the particular entry is stored within the first memory. In response to a determination that the second entry set is stored in the first memory, a search of the second entry set is initiated in order to locate the particular entry. In response to locating the particular entry, the selected nonphysical address is translated to the corresponding physical address utilizing the particular entry. In one embodiment, if the first entry set becomes available during the search of the second entry set, the first entry set is preferentially searched prior to completing the search of the second entry set.

摘要翻译： 公开了一种用于将非物理地址转换为物理地址的处理器和方法。 如果能够包含将选择的非物理地址与分配给数据处理系统中的设备的对应物理地址相关联的特定条目的第一条目集存储在数据处理系统的第一存储器内，则确定。 响应于第一条目集合未被存储在第一存储器中的确定，确定可以包含特定条目的第二条目集是否被存储在第一存储器内。 响应于第二条目集合被存储在第一存储器中的确定，启动第二条目集合的搜索以定位特定条目。 响应于定位特定条目，使用特定条目将所选择的非物理地址转换为相应的物理地址。 在一个实施例中，如果第一条目集合在搜索第二条目集合期间变得可用，则在完成第二条目集合的搜索之前优先地搜索第一条目集合。

公开(公告)号：US5787479A

公开(公告)日：1998-07-28

申请号：US639576

申请日：1996-04-29

申请人： Romesh Mangho Jessani ,  Belliappa Manavattira Kuttanna ,  Soummya Mallick ,  Rajesh Bhikhubhai Patel

发明人： Romesh Mangho Jessani ,  Belliappa Manavattira Kuttanna ,  Soummya Mallick ,  Rajesh Bhikhubhai Patel

IPC分类号： G06F11/00 ,  G06F12/08 ,  G06F12/16

CPC分类号： G06F11/004 ,  G06F12/0859

摘要： A method and system for preventing information corruption in a cache memory due to a bus error which occurs during a cache linefill operation is disclosed. The cache memory includes multiple cache lines, and a tag is associated with each cache line. In accordance with the present disclosure, a tag associated with a cache line is validated before a linefill operation is performed on the cache line. In response to an occurrence of a bus error during the linefill operation, the tag associated with the cache line for which a linefill operation is performed, is invalidated such that the information within the cache line remains valid during a linefill operation unless a bus error occurs.

摘要翻译： 公开了一种用于防止由于在高速缓存行填充操作期间发生的总线错误而在高速缓冲存储器中的信息损坏的方法和系统。 高速缓冲存储器包括多个高速缓存线，并且标签与每个高速缓存线相关联。 根据本公开，在对高速缓存行执行行填充操作之前，与高速缓存行相关联的标签被验证。 响应于在线路填充操作期间发生总线错误，与执行线路填充操作的高速缓存行相关联的标签被无效，使得在行填充操作期间，高速缓存行内的信息保持有效，除非发生总线错误 。